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## Copyright (c) 2006, 2007 Xilinx, Inc.

## This design is confidential and proprietary of Xilinx, All Rights Reserved.

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##   ____  ____

##  /   /\/   /

## /___/  \  /   Vendor:        Xilinx

## \   \   \/    Version:       1.0.1

##  \   \        Filename:      starter_kit_constraints.ucf

##  /   /        Date Created:  December 25, 2006

## /___/   /\    Last Modified: April 1, 2007

## \   \  /  \

##  \___\/\___\

##

## Devices:   Spartan-3 Generation FPGA

## Purpose:   Complete constraint file for Spartan-3A(N) Starter Kit

## Contact:   crabill@xilinx.com

## Reference: None

##

## Revision History:

##   Rev 1.0.0 - (crabill) Created December 25, 2006 for PCB revision C.

##   Rev 1.0.1 - (crabill) Modified April 1, 2007 to mention revision D

##                         of the PCB and applicability to Spartan-3AN.

##

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##

## LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".

## Xilinx and its licensors make and you receive no warranties or conditions,

## express, implied, statutory or otherwise, and Xilinx specifically disclaims

## any implied warranties of merchantability, non-infringement, or fitness for

## a particular purpose. Xilinx does not warrant that the functions contained

## in these designs will meet your requirements, or that the operation of

## these designs will be uninterrupted or error free, or that defects in the

## designs will be corrected. Furthermore, Xilinx does not warrant or make any

## representations regarding use or the results of the use of the designs in

## terms of correctness, accuracy, reliability, or otherwise.

##

## LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable

## for any loss of data, lost profits, cost or procurement of substitute goods

## or services, or for any special, incidental, consequential, or indirect

## damages arising from the use or operation of the designs or accompanying

## documentation, however caused and on any theory of liability. This

## limitation will apply even if Xilinx has been advised of the possibility

## of such damage. This limitation shall apply not-withstanding the failure

## of the essential purpose of any limited remedies herein.

##

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## Copyright (c) 2006, 2007 Xilinx, Inc.

## This design is confidential and proprietary of Xilinx, All Rights Reserved.

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# On this board, VCCAUX is 3.3 volts.

CONFIG VCCAUX = "3.3" ;

# Configure SUSPEND mode options.

CONFIG ENABLE_SUSPEND = "FILTERED" ;

# FILTERED is appropriate for use with the switch on this board. Other allowed

# settings are NO or UNFILTERED.  If set NO, the AWAKE pin becomes general I/O.

# Please read the FPGA User Guide for more information.

# Configure POST_CRC options.

CONFIG POST_CRC = "DISABLE" ;

# DISABLE the post-configuration CRC checking so INIT_B is available for

# general I/O after configuration is done.  On this board, INIT_B is used

# after configuration to control the Platform Flash device.  Other allowed

# settings are ENABLE.  Please read the FPGA User Guide for more information.

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# These are sample constraints for the three clock inputs.  You will need

# to change these constraints to suit your application.  Please read the

# FPGA Development System Reference Guide for more information on expressing

# timing constraints for your design.

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NET "clk"       LOC = "V12"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.830 ;

OFFSET = IN  10.410 VALID 20.830 BEFORE "clk" ;

OFFSET = OUT 20.830 AFTER "clk" ;

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# Accessory Headers (J18, J19, J20)

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#NET "J18_IO<1>"     LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J18_IO<2>"     LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J18_IO<3>"     LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J18_IO<4>"     LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "usbSlaveVP"     LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "usbSlaveVM"     LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "usbSlaveOE_n"     LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "usbDPlusPullup"     LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J19_IO<1>"     LOC = "Y18"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J19_IO<2>"     LOC = "W18"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J19_IO<3>"     LOC = "V17"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J19_IO<4>"     LOC = "W17"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J20_IO<1>"     LOC = "V14"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J20_IO<2>"     LOC = "V15"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J20_IO<3>"     LOC = "W16"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#NET "J20_IO<4>"     LOC = "V16"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

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# 10/100 Ethernet (E)

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NET "E_NRST"        LOC = "D15"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

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# Serial Peripheral System

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NET "SPI_SCK"       LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

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# Parallel Flash (NF)

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NET "NF_CE"         LOC = "W20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

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# DDR2 SDRAM Device (SD)

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NET "SD_CS"         LOC = "M5"   | IOSTANDARD = SSTL18_I ;

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