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Simulator report for usimplez_top
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Wed Nov 09 11:48:19 2011
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Simulator Summary
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3. Simulator Settings
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4. Simulation Waveforms
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5. |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM
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6. Coverage Summary
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7. Complete 1/0-Value Coverage
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8. Missing 1-Value Coverage
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9. Missing 0-Value Coverage
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10. Simulator INI Usage
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11. Simulator Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+--------------------------------------------+
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; Simulator Summary ;
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+-----------------------------+--------------+
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; Type ; Value ;
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+-----------------------------+--------------+
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; Simulation Start Time ; 0 ps ;
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; Simulation End Time ; 100.0 us ;
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; Simulation Netlist Size ; 135 nodes ;
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; Simulation Coverage ; 89.63 % ;
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; Total Number of Transitions ; 113971 ;
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; Simulation Breakpoints ; 0 ;
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; Family ; Stratix II ;
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; Device ; EP2S15F484C3 ;
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+-----------------------------+--------------+
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+-------------------------------------------------------------------------------------------------------------------------+
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; Simulator Settings ;
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+--------------------------------------------------------------------------------------------+------------+---------------+
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; Option ; Setting ; Default Value ;
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+--------------------------------------------------------------------------------------------+------------+---------------+
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; Simulation mode ; Timing ; Timing ;
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; Start time ; 0 ns ; 0 ns ;
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; Simulation results format ; CVWF ; ;
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; Add pins automatically to simulation output waveforms ; On ; On ;
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; Check outputs ; Off ; Off ;
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; Report simulation coverage ; On ; On ;
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; Display complete 1/0 value coverage report ; On ; On ;
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; Display missing 1-value coverage report ; On ; On ;
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; Display missing 0-value coverage report ; On ; On ;
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; Detect setup and hold time violations ; Off ; Off ;
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; Detect glitches ; Off ; Off ;
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; Disable timing delays in Timing Simulation ; Off ; Off ;
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; Generate Signal Activity File ; Off ; Off ;
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; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
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; Group bus channels in simulation results ; Off ; Off ;
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; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
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; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
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; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
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; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
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; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
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+--------------------------------------------------------------------------------------------+------------+---------------+
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+----------------------+
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; Simulation Waveforms ;
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+----------------------+
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Waveform report data cannot be output to ASCII.
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Please use Quartus II to view the waveform report data.
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+-----------------------------------------------------------------------------------------------+
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ;
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+-----------------------------------------------------------------------------------------------+
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Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
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+--------------------------------------------------------------------+
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; Coverage Summary ;
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+-----------------------------------------------------+--------------+
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; Type ; Value ;
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+-----------------------------------------------------+--------------+
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; Total coverage as a percentage ; 89.63 % ;
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; Total nodes checked ; 135 ;
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; Total output ports checked ; 164 ;
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; Total output ports with complete 1/0-value coverage ; 147 ;
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; Total output ports with no 1/0-value coverage ; 17 ;
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; Total output ports with no 1-value coverage ; 17 ;
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; Total output ports with no 0-value coverage ; 17 ;
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+-----------------------------------------------------+--------------+
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The following table displays output ports that toggle between 1 and 0 during simulation.
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Complete 1/0-Value Coverage ;
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+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
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; Node Name ; Output Port Name ; Output Port Type ;
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+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
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; |usimplez_top|usimplez_cpu:cpu|we_o ; |usimplez_top|usimplez_cpu:cpu|we_o ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; regout ;
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| 125 |
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; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; regout ;
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| 126 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; regout ;
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| 127 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; regout ;
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| 128 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; regout ;
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| 129 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; regout ;
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| 130 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; regout ;
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| 132 |
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; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; regout ;
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| 133 |
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; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; regout ;
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| 134 |
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; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; regout ;
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| 135 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[10] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[10] ; regout ;
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| 136 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; regout ;
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[5] ; regout ;
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| 138 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[4] ; regout ;
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| 139 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[3] ; regout ;
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| 140 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[2] ; regout ;
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| 141 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0] ; regout ;
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| 142 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[1] ; regout ;
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| 143 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[11] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[11] ; regout ;
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| 144 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[9] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[9] ; regout ;
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| 145 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[8] ; regout ;
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| 146 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[6] ; regout ;
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| 147 |
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; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[7] ; regout ;
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| 148 |
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; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; regout ;
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| 149 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; regout ;
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| 150 |
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; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; regout ;
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| 151 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; regout ;
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| 152 |
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; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; regout ;
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| 153 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; regout ;
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| 154 |
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; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; regout ;
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| 155 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; regout ;
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| 156 |
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; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; regout ;
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| 157 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; regout ;
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| 158 |
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; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; regout ;
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| 159 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; portadataout0 ;
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| 160 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4 ; portadataout1 ;
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| 161 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5 ; portadataout2 ;
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| 162 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6 ; portadataout3 ;
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| 163 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7 ; portadataout4 ;
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| 164 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8 ; portadataout5 ;
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| 165 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9 ; portadataout6 ;
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| 166 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10 ; portadataout7 ;
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| 167 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11 ; portadataout8 ;
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| 168 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; portadataout0 ;
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| 169 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 ; portadataout1 ;
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| 170 |
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; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2 ; portadataout2 ;
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| 171 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; sumout ;
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| 172 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~3 ; cout ;
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| 173 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; sumout ;
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| 174 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~7 ; cout ;
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| 175 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; sumout ;
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| 176 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~11 ; cout ;
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| 177 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; sumout ;
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| 178 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~15 ; cout ;
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| 179 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; sumout ;
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| 180 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~19 ; cout ;
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| 181 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; sumout ;
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| 182 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~23 ; cout ;
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| 183 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; sumout ;
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| 184 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~27 ; cout ;
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| 185 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; sumout ;
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| 186 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~31 ; cout ;
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| 187 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; sumout ;
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| 188 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~35 ; cout ;
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| 189 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; sumout ;
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| 190 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~39 ; cout ;
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| 191 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; sumout ;
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| 192 |
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; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~43 ; cout ;
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| 193 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; sumout ;
|
| 194 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; sumout ;
|
| 195 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~2 ; cout ;
|
| 196 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; sumout ;
|
| 197 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~6 ; cout ;
|
| 198 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; sumout ;
|
| 199 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~10 ; cout ;
|
| 200 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; sumout ;
|
| 201 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~14 ; cout ;
|
| 202 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; sumout ;
|
| 203 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~18 ; cout ;
|
| 204 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; regout ;
|
| 205 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; regout ;
|
| 206 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; regout ;
|
| 207 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; regout ;
|
| 208 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; regout ;
|
| 209 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; regout ;
|
| 210 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; regout ;
|
| 211 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; regout ;
|
| 212 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; regout ;
|
| 213 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Selector32~0 ; |usimplez_top|usimplez_cpu:cpu|Selector32~0 ; combout ;
|
| 214 |
|
|
; |usimplez_top|usimplez_cpu:cpu|In0_o ; |usimplez_top|usimplez_cpu:cpu|In0_o ; regout ;
|
| 215 |
|
|
; |usimplez_top|usimplez_cpu:cpu|In1_o ; |usimplez_top|usimplez_cpu:cpu|In1_o ; regout ;
|
| 216 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Op0_o ; |usimplez_top|usimplez_cpu:cpu|Op0_o ; regout ;
|
| 217 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Op1_o ; |usimplez_top|usimplez_cpu:cpu|Op1_o ; regout ;
|
| 218 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; regout ;
|
| 219 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; regout ;
|
| 220 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; regout ;
|
| 221 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado~6 ; |usimplez_top|usimplez_cpu:cpu|estado~6 ; combout ;
|
| 222 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Selector10~0 ; |usimplez_top|usimplez_cpu:cpu|Selector10~0 ; combout ;
|
| 223 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; combout ;
|
| 224 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado~7 ; |usimplez_top|usimplez_cpu:cpu|estado~7 ; combout ;
|
| 225 |
|
|
; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; combout ;
|
| 226 |
|
|
; |usimplez_top|usimplez_cpu:cpu|estado~8 ; |usimplez_top|usimplez_cpu:cpu|estado~8 ; combout ;
|
| 227 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; combout ;
|
| 228 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; combout ;
|
| 229 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; combout ;
|
| 230 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; combout ;
|
| 231 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; combout ;
|
| 232 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; combout ;
|
| 233 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; combout ;
|
| 234 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; combout ;
|
| 235 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; combout ;
|
| 236 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; combout ;
|
| 237 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; combout ;
|
| 238 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; combout ;
|
| 239 |
|
|
; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~0 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~0 ; combout ;
|
| 240 |
|
|
; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~1 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~1 ; combout ;
|
| 241 |
|
|
; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~2 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~2 ; combout ;
|
| 242 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~0 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~0 ; combout ;
|
| 243 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~1 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~1 ; combout ;
|
| 244 |
|
|
; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; combout ;
|
| 245 |
|
|
; |usimplez_top|we_o ; |usimplez_top|we_o ; padio ;
|
| 246 |
|
|
; |usimplez_top|in0_o ; |usimplez_top|in0_o ; padio ;
|
| 247 |
|
|
; |usimplez_top|in1_o ; |usimplez_top|in1_o ; padio ;
|
| 248 |
|
|
; |usimplez_top|op0_o ; |usimplez_top|op0_o ; padio ;
|
| 249 |
|
|
; |usimplez_top|op1_o ; |usimplez_top|op1_o ; padio ;
|
| 250 |
|
|
; |usimplez_top|clk_i ; |usimplez_top|clk_i~corein ; combout ;
|
| 251 |
|
|
; |usimplez_top|rst_i ; |usimplez_top|rst_i~corein ; combout ;
|
| 252 |
|
|
; |usimplez_top|clk_i~clkctrl ; |usimplez_top|clk_i~clkctrl ; outclk ;
|
| 253 |
|
|
; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; combout ;
|
| 254 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; combout ;
|
| 255 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; combout ;
|
| 256 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; combout ;
|
| 257 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; combout ;
|
| 258 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; combout ;
|
| 259 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; combout ;
|
| 260 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; combout ;
|
| 261 |
|
|
; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; combout ;
|
| 262 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; combout ;
|
| 263 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; combout ;
|
| 264 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; combout ;
|
| 265 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; combout ;
|
| 266 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; combout ;
|
| 267 |
|
|
+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
|
| 268 |
|
|
|
| 269 |
|
|
|
| 270 |
|
|
The following table displays output ports that do not toggle to 1 during simulation.
|
| 271 |
|
|
+----------------------------------------------------------------------------------------------------------------+
|
| 272 |
|
|
; Missing 1-Value Coverage ;
|
| 273 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 274 |
|
|
; Node Name ; Output Port Name ; Output Port Type ;
|
| 275 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 276 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;
|
| 277 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;
|
| 278 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;
|
| 279 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;
|
| 280 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;
|
| 281 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;
|
| 282 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;
|
| 283 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;
|
| 284 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;
|
| 285 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;
|
| 286 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;
|
| 287 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;
|
| 288 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;
|
| 289 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;
|
| 290 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;
|
| 291 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;
|
| 292 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;
|
| 293 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
The following table displays output ports that do not toggle to 0 during simulation.
|
| 297 |
|
|
+----------------------------------------------------------------------------------------------------------------+
|
| 298 |
|
|
; Missing 0-Value Coverage ;
|
| 299 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 300 |
|
|
; Node Name ; Output Port Name ; Output Port Type ;
|
| 301 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 302 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;
|
| 303 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;
|
| 304 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;
|
| 305 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;
|
| 306 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;
|
| 307 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;
|
| 308 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;
|
| 309 |
|
|
; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;
|
| 310 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;
|
| 311 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;
|
| 312 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;
|
| 313 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;
|
| 314 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;
|
| 315 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;
|
| 316 |
|
|
; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;
|
| 317 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;
|
| 318 |
|
|
; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;
|
| 319 |
|
|
+----------------------------------------------+----------------------------------------------+------------------+
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
+---------------------+
|
| 323 |
|
|
; Simulator INI Usage ;
|
| 324 |
|
|
+--------+------------+
|
| 325 |
|
|
; Option ; Usage ;
|
| 326 |
|
|
+--------+------------+
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
+--------------------+
|
| 330 |
|
|
; Simulator Messages ;
|
| 331 |
|
|
+--------------------+
|
| 332 |
|
|
Info: *******************************************************************
|
| 333 |
|
|
Info: Running Quartus II Simulator
|
| 334 |
|
|
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
|
| 335 |
|
|
Info: Processing started: Wed Nov 09 11:48:14 2011
|
| 336 |
|
|
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top
|
| 337 |
|
|
Info: Using vector source file "C:/Altera/qdesigns/usimplez00/usimplez_top.vwf"
|
| 338 |
|
|
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
|
| 339 |
|
|
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
|
| 340 |
|
|
Info: Simulation partitioned into 1 sub-simulations
|
| 341 |
|
|
Info: Simulation coverage is 89.63 %
|
| 342 |
|
|
Info: Number of transitions in simulation is 113971
|
| 343 |
|
|
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
|
| 344 |
|
|
Info: Peak virtual memory: 121 megabytes
|
| 345 |
|
|
Info: Processing ended: Wed Nov 09 11:48:24 2011
|
| 346 |
|
|
Info: Elapsed time: 00:00:10
|
| 347 |
|
|
Info: Total CPU time (on all processors): 00:00:10
|
| 348 |
|
|
|
| 349 |
|
|
|
