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sonicwave |
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-- Company: University of Southern Denmark
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-- Engineer: Simon Falsig
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--
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-- Create Date: 19/03/2010
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-- Design Name: uTosNet
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-- Module Name: uTosNet_usb - Behavioral
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-- File Name: uTosNet_uart.vhd
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-- Project Name: uTosNet
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-- Target Devices: SDU XC3S50AN Board
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-- Tool versions: Xilinx ISE 11.4
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-- Description: This module implements a very simple ASCII based protocol over
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-- a uart. Data can be read and written from and to one port of a
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-- dual-port blockRAM, where the other blockRAM port is available
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-- to the user application. Communication takes place at the fol-
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-- lowing settings:
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-- Baudrate: 115200 kbps
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-- Parity: none
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-- Bits: 8 data bits, 1 stop bit
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-- Flowcontrol: none
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-- The protocol format can be seen in the documentation files.
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--
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-- Focus has mostly been on a simple implementation, as the
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-- module is to be used during courses at the university.
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--
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-- Dependencies: The module uses the uart implementation from Ken Chapmans
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-- PicoBlaze. More specifically the following files:
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-- uart_rx.vhd
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-- kcuart_rx.vhd
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-- bbfifo_16x8.vhd
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-- uart_tx.vhd
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-- kcuart_tx.vhd
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-- These files can be downloaded from Xilinx:
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-- https://secure.xilinx.com/webreg/register.do?group=picoblaze
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--
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-- It should not be hard to implement the module using another
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-- uart implementation though.
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--
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-- Revision:
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-- Revision 0.10 - Initial release
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity uTosNet_uart is
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Port ( clk_50M : in STD_LOGIC;
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serial_out : out STD_LOGIC;
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serial_in : in STD_LOGIC;
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dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
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dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
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dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
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dataReg_clk : in STD_LOGIC;
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dataReg_writeEnable : in STD_LOGIC);
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end uTosNet_uart;
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architecture Behavioral of uTosNet_uart is
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component dataRegister
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Port ( clka : in STD_LOGIC;
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wea : in STD_LOGIC_VECTOR(0 downto 0);
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addra : in STD_LOGIC_VECTOR(5 downto 0);
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dina : in STD_LOGIC_VECTOR(31 downto 0);
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douta : out STD_LOGIC_VECTOR(31 downto 0);
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clkb : in STD_LOGIC;
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web : in STD_LOGIC_VECTOR(0 downto 0);
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addrb : in STD_LOGIC_VECTOR(5 downto 0);
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dinb : in STD_LOGIC_VECTOR(31 downto 0);
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doutb : out STD_LOGIC_VECTOR(31 downto 0));
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end component;
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component uart_rx
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Port ( serial_in : in STD_LOGIC;
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data_out : out STD_LOGIC_VECTOR(7 downto 0);
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read_buffer : in STD_LOGIC;
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reset_buffer : in STD_LOGIC;
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en_16_x_baud : in STD_LOGIC;
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buffer_data_present : out STD_LOGIC;
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buffer_full : out STD_LOGIC;
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buffer_half_full : out STD_LOGIC;
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clk : in STD_LOGIC);
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end component;
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component uart_tx
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Port ( serial_out : out STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR(7 downto 0);
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write_buffer : in STD_LOGIC;
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reset_buffer : in STD_LOGIC;
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en_16_x_baud : in STD_LOGIC;
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buffer_full : out STD_LOGIC;
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buffer_half_full : out STD_LOGIC;
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clk : in STD_LOGIC);
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end component;
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signal baudCount : integer range 0 to 36 :=0;
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signal en_16_x_baud : STD_LOGIC;
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signal readFromUart : STD_LOGIC;
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signal rxData : STD_LOGIC_VECTOR(7 downto 0);
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signal rxDataPresent : STD_LOGIC;
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signal rxFull : STD_LOGIC;
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signal rxHalfFull : STD_LOGIC;
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signal txData : STD_LOGIC_VECTOR(7 downto 0);
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signal writeToUart : STD_LOGIC;
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signal txFull : STD_LOGIC;
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signal txHalfFull : STD_LOGIC;
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constant UARTDIV : STD_LOGIC_VECTOR(5 downto 0) := "011010";
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type STATES is (IDLE, COMMAND_IN, WAIT1, REG_IN, WAIT2, INDEX_IN, WAIT3, SPACE_IN, WAIT4, DATA_IN, WAIT_DATA_IN, DATA_OUT, PERFORM_READ_SETUP, PERFORM_READ_CLK, PERFORM_READ_DONE, PERFORM_WRITE_SETUP, PERFORM_WRITE_CLK, PERFORM_WRITE_DONE);
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signal state : STATES := IDLE;
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signal nextState : STATES := IDLE;
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type COMMANDS is (CMD_NONE, CMD_READ, CMD_WRITE, CMD_COMMIT_READ, CMD_COMMIT_WRITE);
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signal currentCommand : COMMANDS := CMD_NONE;
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signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
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signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
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signal int_dataReg_clk : STD_LOGIC;
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signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
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signal inputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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signal outputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
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signal readCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
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signal writeCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
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signal currentReg : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
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signal currentIndex : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
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signal commitRead : STD_LOGIC := '0';
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signal commitWrite : STD_LOGIC := '0';
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begin
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dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
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dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
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Port map ( clka => dataReg_clk, --PortA is used for the user application
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wea => dataReg_writeEnable_V, --
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addra => dataReg_addr, --
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dina => dataReg_dataIn, --
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douta => dataReg_dataOut, --
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clkb => int_dataReg_clk, --PortB is used for the SPI interface
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web => int_dataReg_we, --
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addrb => int_dataReg_addr, --
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dinb => int_dataReg_dataIn, --
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doutb => int_dataReg_dataOut); --
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rx_inst: uart_rx
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Port map ( serial_in => serial_in,
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data_out => rxData,
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read_buffer => readFromUart,
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reset_buffer => '0',
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en_16_x_baud => en_16_x_baud,
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buffer_data_present => rxDataPresent,
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buffer_full => rxFull,
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buffer_half_full => rxHalfFull,
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clk => clk_50M );
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tx_inst : uart_tx
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Port map ( serial_out => serial_out,
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data_in => txData,
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write_buffer => writeToUart,
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reset_buffer => '0',
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en_16_x_baud => en_16_x_baud,
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buffer_full => txFull,
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buffer_half_full => txHalfFull,
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clk => clk_50M);
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baudTimer_inst: process(clk_50M)
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begin
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if(clk_50M'event and clk_50M='1')then
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if(baudCount = UARTDIV)then
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baudCount <= 0;
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en_16_x_baud <= '1';
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else
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baudCount <= baudCount + 1;
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en_16_x_baud <= '0';
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end if;
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end if;
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end process baudTimer_inst;
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process(clk_50M)
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begin
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if(clk_50M = '1' and clk_50M'event) then
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state <= nextState;
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readFromUart <= '0';
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writeToUart <= '0';
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case state is
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when IDLE =>
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currentCommand <= CMD_NONE;
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readCounter <= (others => '0');
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writeCounter <= (others => '0');
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commitRead <= '0';
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commitWrite <= '0';
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when COMMAND_IN =>
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commitRead <= '0';
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commitWrite <= '0';
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if(rxDataPresent = '1') then
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case rxData is
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when "01110010" => --'r'
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currentCommand <= CMD_READ;
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when "01110111" => --'w'
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currentCommand <= CMD_WRITE;
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when "01110100" => --'t'
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commitRead <= '1'; --Might need to switch with write
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currentCommand <= CMD_NONE;
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when "01100011" => --'c'
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commitWrite <= '1'; --Might need to switch with read
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currentCommand <= CMD_NONE;
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when others =>
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currentCommand <= CMD_NONE;
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end case;
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readFromUart <= '1';
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end if;
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when WAIT1 =>
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when REG_IN =>
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if(rxDataPresent = '1') then
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case rxData is
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when "00110000" =>
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currentReg <= "000";
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when "00110001" =>
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currentReg <= "001";
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when "00110010" =>
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currentReg <= "010";
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when "00110011" =>
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currentReg <= "011";
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when "00110100" =>
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currentReg <= "100";
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when "00110101" =>
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currentReg <= "101";
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when "00110110" =>
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currentReg <= "110";
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when "00110111" =>
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currentReg <= "111";
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when others =>
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currentCommand <= CMD_NONE;
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end case;
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readFromUart <= '1';
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end if;
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when WAIT2 =>
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when INDEX_IN =>
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if(rxDataPresent = '1') then
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case rxData is
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when "00110000" =>
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currentIndex <= "000";
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when "00110001" =>
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currentIndex <= "001";
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when "00110010" =>
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currentIndex <= "010";
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when "00110011" =>
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currentIndex <= "011";
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when "00110100" =>
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currentIndex <= "100";
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when "00110101" =>
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currentIndex <= "101";
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when "00110110" =>
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currentIndex <= "110";
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when "00110111" =>
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currentIndex <= "111";
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when others =>
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currentCommand <= CMD_NONE;
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end case;
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readFromUart <= '1';
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end if;
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when WAIT3 =>
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when SPACE_IN =>
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if(rxDataPresent = '1') then
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if(not(rxData = "00100000")) then
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currentCommand <= CMD_NONE;
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end if;
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readFromUart <= '1';
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end if;
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when WAIT4 =>
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when DATA_IN =>
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if(rxDataPresent = '1') then
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case rxData is
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when "00110000" => --'0'
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inputBuffer <= inputBuffer(27 downto 0) & "0000";
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when "00110001" => --'1'
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inputBuffer <= inputBuffer(27 downto 0) & "0001";
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when "00110010" => --'2'
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inputBuffer <= inputBuffer(27 downto 0) & "0010";
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when "00110011" => --'3'
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inputBuffer <= inputBuffer(27 downto 0) & "0011";
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when "00110100" => --'4'
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inputBuffer <= inputBuffer(27 downto 0) & "0100";
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when "00110101" => --'5'
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inputBuffer <= inputBuffer(27 downto 0) & "0101";
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when "00110110" => --'6'
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inputBuffer <= inputBuffer(27 downto 0) & "0110";
|
| 323 |
|
|
when "00110111" => --'7'
|
| 324 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "0111";
|
| 325 |
|
|
when "00111000" => --'8'
|
| 326 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1000";
|
| 327 |
|
|
when "00111001" => --'9'
|
| 328 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1001";
|
| 329 |
|
|
when "01100001" => --'a'
|
| 330 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1010";
|
| 331 |
|
|
when "01100010" => --'b'
|
| 332 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1011";
|
| 333 |
|
|
when "01100011" => --'c'
|
| 334 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1100";
|
| 335 |
|
|
when "01100100" => --'d'
|
| 336 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1101";
|
| 337 |
|
|
when "01100101" => --'e'
|
| 338 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1110";
|
| 339 |
|
|
when "01100110" => --'f'
|
| 340 |
|
|
inputBuffer <= inputBuffer(27 downto 0) & "1111";
|
| 341 |
|
|
when others =>
|
| 342 |
|
|
currentCommand <= CMD_NONE;
|
| 343 |
|
|
end case;
|
| 344 |
|
|
readFromUart <= '1';
|
| 345 |
|
|
readCounter <= readCounter + 1;
|
| 346 |
|
|
end if;
|
| 347 |
|
|
when WAIT_DATA_IN =>
|
| 348 |
|
|
when DATA_OUT =>
|
| 349 |
|
|
writeToUart <= '1';
|
| 350 |
|
|
if(writeCounter = 8) then
|
| 351 |
|
|
txData <= "00100000"; --Transmit a space to make thinks look nicer...:)
|
| 352 |
|
|
else
|
| 353 |
|
|
case outputBuffer(31 downto 28) is
|
| 354 |
|
|
when "0000" => --'0'
|
| 355 |
|
|
txData <= "00110000";
|
| 356 |
|
|
when "0001" => --'1'
|
| 357 |
|
|
txData <= "00110001";
|
| 358 |
|
|
when "0010" => --'2'
|
| 359 |
|
|
txData <= "00110010";
|
| 360 |
|
|
when "0011" => --'3'
|
| 361 |
|
|
txData <= "00110011";
|
| 362 |
|
|
when "0100" => --'4'
|
| 363 |
|
|
txData <= "00110100";
|
| 364 |
|
|
when "0101" => --'5'
|
| 365 |
|
|
txData <= "00110101";
|
| 366 |
|
|
when "0110" => --'6'
|
| 367 |
|
|
txData <= "00110110";
|
| 368 |
|
|
when "0111" => --'7'
|
| 369 |
|
|
txData <= "00110111";
|
| 370 |
|
|
when "1000" => --'8'
|
| 371 |
|
|
txData <= "00111000";
|
| 372 |
|
|
when "1001" => --'9'
|
| 373 |
|
|
txData <= "00111001";
|
| 374 |
|
|
when "1010" => --'a'
|
| 375 |
|
|
txData <= "01100001";
|
| 376 |
|
|
when "1011" => --'b'
|
| 377 |
|
|
txData <= "01100010";
|
| 378 |
|
|
when "1100" => --'c'
|
| 379 |
|
|
txData <= "01100011";
|
| 380 |
|
|
when "1101" => --'d'
|
| 381 |
|
|
txData <= "01100100";
|
| 382 |
|
|
when "1110" => --'e'
|
| 383 |
|
|
txData <= "01100101";
|
| 384 |
|
|
when "1111" => --'f'
|
| 385 |
|
|
txData <= "01100110";
|
| 386 |
|
|
when others =>
|
| 387 |
|
|
end case;
|
| 388 |
|
|
end if;
|
| 389 |
|
|
outputBuffer <= outputBuffer(27 downto 0) & "0000";
|
| 390 |
|
|
writeCounter <= writeCounter + 1;
|
| 391 |
|
|
when PERFORM_READ_SETUP =>
|
| 392 |
|
|
int_dataReg_addr <= currentReg & currentIndex;
|
| 393 |
|
|
int_dataReg_we <= "0";
|
| 394 |
|
|
int_dataReg_clk <= '0';
|
| 395 |
|
|
when PERFORM_READ_CLK =>
|
| 396 |
|
|
int_dataReg_clk <= '1';
|
| 397 |
|
|
when PERFORM_READ_DONE =>
|
| 398 |
|
|
outputBuffer <= int_dataReg_dataOut;
|
| 399 |
|
|
int_dataReg_clk <= '0';
|
| 400 |
|
|
when PERFORM_WRITE_SETUP =>
|
| 401 |
|
|
int_dataReg_addr <= currentReg & currentIndex;
|
| 402 |
|
|
int_dataReg_dataIn <= inputBuffer;
|
| 403 |
|
|
int_dataReg_we <= "1";
|
| 404 |
|
|
int_dataReg_clk <= '0';
|
| 405 |
|
|
when PERFORM_WRITE_CLK =>
|
| 406 |
|
|
int_dataReg_clk <= '1';
|
| 407 |
|
|
when PERFORM_WRITE_DONE =>
|
| 408 |
|
|
int_dataReg_we <= "0";
|
| 409 |
|
|
int_dataReg_clk <= '0';
|
| 410 |
|
|
end case;
|
| 411 |
|
|
end if;
|
| 412 |
|
|
end process;
|
| 413 |
|
|
|
| 414 |
|
|
process(state, rxDataPresent, currentCommand, readCounter, writeCounter)
|
| 415 |
|
|
begin
|
| 416 |
|
|
if((currentCommand = CMD_NONE) and not ((state = COMMAND_IN) or (state = IDLE))) then
|
| 417 |
|
|
nextState <= IDLE;
|
| 418 |
|
|
else
|
| 419 |
|
|
case state is
|
| 420 |
|
|
when IDLE =>
|
| 421 |
|
|
nextState <= COMMAND_IN;
|
| 422 |
|
|
when COMMAND_IN =>
|
| 423 |
|
|
if(rxDataPresent = '1') then
|
| 424 |
|
|
nextState <= WAIT1;
|
| 425 |
|
|
else
|
| 426 |
|
|
nextState <= COMMAND_IN;
|
| 427 |
|
|
end if;
|
| 428 |
|
|
when WAIT1 =>
|
| 429 |
|
|
if(rxDataPresent = '0') then
|
| 430 |
|
|
nextState <= REG_IN;
|
| 431 |
|
|
else
|
| 432 |
|
|
nextState <= WAIT1;
|
| 433 |
|
|
end if;
|
| 434 |
|
|
when REG_IN =>
|
| 435 |
|
|
if(rxDataPresent = '1') then
|
| 436 |
|
|
nextState <= WAIT2;
|
| 437 |
|
|
else
|
| 438 |
|
|
nextState <= REG_IN;
|
| 439 |
|
|
end if;
|
| 440 |
|
|
when WAIT2 =>
|
| 441 |
|
|
if(rxDataPresent = '0') then
|
| 442 |
|
|
nextState <= INDEX_IN;
|
| 443 |
|
|
else
|
| 444 |
|
|
nextState <= WAIT2;
|
| 445 |
|
|
end if;
|
| 446 |
|
|
when INDEX_IN =>
|
| 447 |
|
|
if(rxDataPresent = '1') then
|
| 448 |
|
|
nextState <= WAIT3;
|
| 449 |
|
|
else
|
| 450 |
|
|
nextState <= INDEX_IN;
|
| 451 |
|
|
end if;
|
| 452 |
|
|
when WAIT3 =>
|
| 453 |
|
|
if(rxDataPresent = '0') then
|
| 454 |
|
|
if(currentCommand = CMD_READ) then
|
| 455 |
|
|
nextState <= PERFORM_READ_SETUP;
|
| 456 |
|
|
else
|
| 457 |
|
|
nextState <= SPACE_IN;
|
| 458 |
|
|
end if;
|
| 459 |
|
|
else
|
| 460 |
|
|
nextState <= WAIT3;
|
| 461 |
|
|
end if;
|
| 462 |
|
|
when SPACE_IN =>
|
| 463 |
|
|
if(rxDataPresent = '1') then
|
| 464 |
|
|
nextState <= WAIT4;
|
| 465 |
|
|
else
|
| 466 |
|
|
nextState <= SPACE_IN;
|
| 467 |
|
|
end if;
|
| 468 |
|
|
when WAIT4 =>
|
| 469 |
|
|
if(rxDataPresent = '0') then
|
| 470 |
|
|
nextState <= DATA_IN;
|
| 471 |
|
|
else
|
| 472 |
|
|
nextState <= WAIT4;
|
| 473 |
|
|
end if;
|
| 474 |
|
|
when DATA_IN =>
|
| 475 |
|
|
if(rxDataPresent = '1') then
|
| 476 |
|
|
nextState <= WAIT_DATA_IN;
|
| 477 |
|
|
else
|
| 478 |
|
|
nextState <= DATA_IN;
|
| 479 |
|
|
end if;
|
| 480 |
|
|
when WAIT_DATA_IN =>
|
| 481 |
|
|
if(rxDataPresent = '0') then
|
| 482 |
|
|
if(readCounter = 8) then
|
| 483 |
|
|
nextState <= PERFORM_WRITE_SETUP;
|
| 484 |
|
|
else
|
| 485 |
|
|
nextState <= DATA_IN;
|
| 486 |
|
|
end if;
|
| 487 |
|
|
else
|
| 488 |
|
|
nextState <= WAIT_DATA_IN;
|
| 489 |
|
|
end if;
|
| 490 |
|
|
when DATA_OUT =>
|
| 491 |
|
|
if(writeCounter = 8) then
|
| 492 |
|
|
nextState <= IDLE;
|
| 493 |
|
|
else
|
| 494 |
|
|
nextState <= DATA_OUT;
|
| 495 |
|
|
end if;
|
| 496 |
|
|
when PERFORM_READ_SETUP =>
|
| 497 |
|
|
nextState <= PERFORM_READ_CLK;
|
| 498 |
|
|
when PERFORM_READ_CLK =>
|
| 499 |
|
|
nextState <= PERFORM_READ_DONE;
|
| 500 |
|
|
when PERFORM_READ_DONE =>
|
| 501 |
|
|
nextState <= DATA_OUT;
|
| 502 |
|
|
when PERFORM_WRITE_SETUP =>
|
| 503 |
|
|
nextState <= PERFORM_WRITE_CLK;
|
| 504 |
|
|
when PERFORM_WRITE_CLK =>
|
| 505 |
|
|
nextState <= PERFORM_WRITE_DONE;
|
| 506 |
|
|
when PERFORM_WRITE_DONE =>
|
| 507 |
|
|
nextState <= IDLE;
|
| 508 |
|
|
end case;
|
| 509 |
|
|
end if;
|
| 510 |
|
|
end process;
|
| 511 |
|
|
|
| 512 |
|
|
end Behavioral;
|
| 513 |
|
|
|
