Subversion Repositories utosnet

/*******************************************************************************

*     This file is owned and controlled by Xilinx and must be used             *

*     solely for design, simulation, implementation and creation of            *

*     design files limited to Xilinx devices or technologies. Use              *

*     with non-Xilinx devices or technologies is expressly prohibited          *

*     and immediately terminates your license.                                 *

*                                                                              *

*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *

*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *

*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *

*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *

*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *

*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *

*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *

*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *

*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *

*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *

*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *

*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *

*     FOR A PARTICULAR PURPOSE.                                                *

*                                                                              *

*     Xilinx products are not intended for use in life support                 *

*     appliances, devices, or systems. Use in such applications are            *

*     expressly prohibited.                                                    *

*                                                                              *

*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *

*     All rights reserved.                                                     *

*******************************************************************************/

// The following must be inserted into your Verilog file for this

// core to be instantiated. Change the instance name and port connections

// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

dataRegister YourInstanceName (

        .clka(clka),

        .wea(wea), // Bus [0 : 0]

        .addra(addra), // Bus [5 : 0]

        .dina(dina), // Bus [31 : 0]

        .douta(douta), // Bus [31 : 0]

        .clkb(clkb),

        .web(web), // Bus [0 : 0]

        .addrb(addrb), // Bus [5 : 0]

        .dinb(dinb), // Bus [31 : 0]

        .doutb(doutb)); // Bus [31 : 0]

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file dataRegister.v when simulating

// the core, dataRegister. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".