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The .xco files are created by CoreGen for the following FPGA device:
 
  Xilinx xc3s50an tqg144
 
 
To generate an ip-core for other devices, use the following cores and settings:
 
 
data_register:
- Core:                         Block Memory Generator
- Memory Type:                  True Dual Port RAM
- Use Byte Write Enable:        No
- Algorithm:                    Minimum Area
- Port A:
  - Write Width:                32
  - Write Depth:                64
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Port B:
  - Write Width:                32
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Optional Output Registers:    No
- Memory Initialization:        Fill with 0
- Output Reset Pins:            No

Line No.	Rev	Author	Line
1	10	sonicwave	`The .xco files are created by CoreGen for the following FPGA device:`
2
3			`Xilinx xc3s50an tqg144`
4
5
6			`To generate an ip-core for other devices, use the following cores and settings:`
7
8
9			`data_register:`
10			`- Core: Block Memory Generator`
11			`- Memory Type: True Dual Port RAM`
12			`- Use Byte Write Enable: No`
13			`- Algorithm: Minimum Area`
14			`- Port A:`
15			`- Write Width: 32`
16			`- Write Depth: 64`
17			`- Operating Mode: Write First`
18			`- Enable: Always Enabled`
19			`- Port B:`
20			`- Write Width: 32`
21			`- Operating Mode: Write First`
22			`- Enable: Always Enabled`
23			`- Optional Output Registers: No`
24			`- Memory Initialization: Fill with 0`
25			`- Output Reset Pins: No`

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[/] [utosnet/] [trunk/] [gateware/] [uTosNet_uart/] [readme_ip_xc3s50an_tqg144.txt] - Blame information for rev 10