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121 |
ultro |
# Generated by makeXDC.ulp developed by Sven Raiser, Tuebingen, Germany
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#
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# Board: Y:/__ESA11/ESA11-7a100t/PCBcart 2015_06_26/ESA11-7a100t-V1.1.brd
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# Part Name: FPGA
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# Part pkg: BGA484
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# Created: 03.01.2016 20:22:12
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# Edited: 2016-01-03, by emu
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set_property CFGBVS VCCO [current_design]
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#where value1 is either VCCO or GND
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12 |
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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#where value2 is the voltage provided to configuration bank 0
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#
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# System Clock, Reset
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#
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#set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVTTL} [get_ports 50MHZ] ; will be removed on later boards
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19 |
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVDS_25} [get_ports i_100MHz_N]
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVDS_25} [get_ports i_100MHz_P]
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21 |
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set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVTTL} [get_ports rstn]
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#
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# LEDs
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#
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set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVTTL} [get_ports {gpioA[0]}]
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVTTL} [get_ports {gpioA[1]}]
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set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVTTL} [get_ports {gpioA[3]}]
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#
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# UARTs
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#
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#set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVTTL} [get_ports UART1_CTS_N]
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#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVTTL} [get_ports UART1_RTS_N]
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set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVTTL} [get_ports {RXD}]
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set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVTTL} [get_ports {TXD}]
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#set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVTTL} [get_ports UART2_CTS_N]
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#set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVTTL} [get_ports UART2_RTS_N]
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#set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVTTL} [get_ports TXD]
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#set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVTTL} [get_ports RXD]
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41 |
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#set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVTTL} [get_ports {gpioA[3]}]
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42 |
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#
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# FLASH SPI 256MBIT
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#
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46 |
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#set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVTTL} [get_ports sdclk]
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports sdout]
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set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports sdin]
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49 |
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set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports sdcs]
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#
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# VGA
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#
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#set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVTTL} [get_ports VGA_BLANK_N]
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#set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[0]}]
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56 |
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#set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[1]}]
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#set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[2]}]
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#set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[3]}]
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#set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[4]}]
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#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[5]}]
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#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[6]}]
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#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVTTL} [get_ports {VGA_BLUE[7]}]
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#set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVTTL} [get_ports VGA_CLOCK_P]
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#set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[0]}]
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#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[1]}]
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#set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[2]}]
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#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[3]}]
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#set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[4]}]
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69 |
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#set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[5]}]
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70 |
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#set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[6]}]
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#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVTTL} [get_ports {VGA_GREEN[7]}]
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72 |
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#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVTTL} [get_ports VGA_HSYNC]
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#set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVTTL} [get_ports {VGA_RED[0]}]
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#set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVTTL} [get_ports {VGA_RED[1]}]
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#set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVTTL} [get_ports {VGA_RED[2]}]
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#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVTTL} [get_ports {VGA_RED[3]}]
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#set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVTTL} [get_ports {VGA_RED[4]}]
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#set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVTTL} [get_ports {VGA_RED[5]}]
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#set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVTTL} [get_ports {VGA_RED[6]}]
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#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVTTL} [get_ports {VGA_RED[7]}]
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#set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVTTL} [get_ports VGA_SYNC_N]
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#set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVTTL} [get_ports VGA_VSYNC]
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#
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# PS/2
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#
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#set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVTTL} [get_ports PS2_A_CLK]
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#set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVTTL} [get_ports PS2_A_DATA]
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89 |
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#set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVTTL} [get_ports PS2_B_CLK]
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#set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVTTL} [get_ports PS2_B_DATA]
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#
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# EXPMODs
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#
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#set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVTTL} [get_ports {EXPMOD1[1]}]
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96 |
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#set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVTTL} [get_ports {EXPMOD1[2]}]
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97 |
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#set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVTTL} [get_ports {EXPMOD1[3]}]
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98 |
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#set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVTTL} [get_ports {EXPMOD1[4]}]
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99 |
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#set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVTTL} [get_ports {EXPMOD1[5]}]
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#set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVTTL} [get_ports {EXPMOD1[6]}]
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101 |
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#set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVTTL} [get_ports {EXPMOD1[7]}]
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102 |
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#set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVTTL} [get_ports {EXPMOD1[8]}]
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103 |
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#set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVTTL} [get_ports {EXPMOD2[1]}]
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104 |
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#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVTTL} [get_ports {EXPMOD2[2]}]
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105 |
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#set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVTTL} [get_ports {EXPMOD2[3]}]
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106 |
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#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVTTL} [get_ports {EXPMOD2[4]}]
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107 |
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#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVTTL} [get_ports {EXPMOD2[5]}]
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108 |
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#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVTTL} [get_ports {EXPMOD2[6]}]
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109 |
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#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVTTL} [get_ports {EXPMOD2[7]}]
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110 |
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#set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVTTL} [get_ports {EXPMOD2[8]}]
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111 |
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112 |
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#
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113 |
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# SD-Flash on FPGA
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#
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115 |
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#set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVTTL} [get_ports FPGA_SD_CDET_N]
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVTTL} [get_ports { gpioA[6] }]
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVTTL} [get_ports { gpioA[7] }]
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVTTL} [get_ports { gpioA[5] }]
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#set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVTTL} [get_ports FPGA_SD_D2]
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set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVTTL} [get_ports { gpioA[2] }]
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set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVTTL} [get_ports { gpioA[4] }]
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#
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# Digital Video
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#
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127 |
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set_property -dict {PACKAGE_PIN U21 IOSTANDARD TMDS_33} [get_ports VID_CLK_N]
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128 |
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set_property -dict {PACKAGE_PIN T21 IOSTANDARD TMDS_33} [get_ports VID_CLK_P]
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129 |
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD TMDS_33} [get_ports {VID_D_N[0]}]
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130 |
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set_property -dict {PACKAGE_PIN P19 IOSTANDARD TMDS_33} [get_ports {VID_D_P[0]}]
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set_property -dict {PACKAGE_PIN R21 IOSTANDARD TMDS_33} [get_ports {VID_D_N[1]}]
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD TMDS_33} [get_ports {VID_D_P[1]}]
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set_property -dict {PACKAGE_PIN V22 IOSTANDARD TMDS_33} [get_ports {VID_D_N[2]}]
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set_property -dict {PACKAGE_PIN U22 IOSTANDARD TMDS_33} [get_ports {VID_D_P[2]}]
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#set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVTTL} [get_ports VID_RSCL]
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#set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVTTL} [get_ports VID_RSDA]
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137 |
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138 |
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#
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139 |
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# Ethernet PHY DP83848, RMII only
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140 |
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#
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141 |
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#set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVTTL} [get_ports ETH1_CLK]
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142 |
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#set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVTTL} [get_ports ETH1_CRS_DEV]
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143 |
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#set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVTTL} [get_ports ETH1_MDC]
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144 |
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#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVTTL} [get_ports ETH1_MDIO]
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145 |
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#set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVTTL} [get_ports ETH1_RST_N]
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146 |
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#set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVTTL} [get_ports {ETH1_RXD[0]}]
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147 |
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#set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVTTL} [get_ports {ETH1_RXD[1]}]
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148 |
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#set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVTTL} [get_ports {ETH1_TXD[0]}]
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149 |
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#set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVTTL} [get_ports {ETH1_TXD[1]}]
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150 |
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#set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVTTL} [get_ports ETH1_TX_EN]
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152 |
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#
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153 |
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# PWM Audio
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154 |
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#
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155 |
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#set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVTTL} [get_ports AUDIO_L]
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156 |
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#set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVTTL} [get_ports AUDIO_R]
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157 |
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158 |
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#
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159 |
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# USB Phy USB3340
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160 |
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#
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161 |
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#set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVTTL} [get_ports USB_CLK]
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162 |
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#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVTTL} [get_ports {USB_D[0]}]
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163 |
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#set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVTTL} [get_ports {USB_D[1]}]
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164 |
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#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVTTL} [get_ports {USB_D[2]}]
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165 |
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#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVTTL} [get_ports {USB_D[3]}]
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166 |
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#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVTTL} [get_ports {USB_D[4]}]
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167 |
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#set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVTTL} [get_ports {USB_D[5]}]
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168 |
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#set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVTTL} [get_ports {USB_D[6]}]
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169 |
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#set_property -dict {PACKAGE_PIN AB13 IOSTANDARD LVTTL} [get_ports {USB_D[7]}]
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170 |
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#set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVTTL} [get_ports USB_DIR]
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171 |
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#set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVTTL} [get_ports USB_NXT]
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172 |
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#set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVTTL} [get_ports USB_OC]
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173 |
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#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVTTL} [get_ports USB_RESET]
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174 |
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#set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVTTL} [get_ports USB_STP]
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175 |
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176 |
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177 |
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#
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178 |
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# Atmel MCU Communication
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179 |
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#
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180 |
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#set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVTTL} [get_ports FPGA_CCLK/CONF_DCLK]
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181 |
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#set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVTTL} [get_ports FPGA_CCLK_INTERNAL]
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182 |
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#set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports FPGA_CSO]
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183 |
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#set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVTTL} [get_ports FPGA_DONE/CONF_DONE]
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184 |
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#set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVTTL} [get_ports FPGA_INIT/CONF_NCONFIG]
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185 |
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186 |
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#set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVTTL} [get_ports FPGA_MISO/CONF_DATA0]
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187 |
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#set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports FPGA_MISO_INTERNAL]
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188 |
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#set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports FPGA_MOSI]
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189 |
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#set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVTTL} [get_ports FPGA_PROG/CONF_NSTATUS]
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190 |
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191 |
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#set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVTTL} [get_ports MCU_SD_CMD/MOSI]
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192 |
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#set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVTTL} [get_ports MCU_SD_D0/MISO]
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193 |
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#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVTTL} [get_ports MCU_SD_D3/SS1]
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194 |
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#set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVTTL} [get_ports MCU_SD_SCLK//SCK]
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195 |
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196 |
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#set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVTTL} [get_ports SS2/FPGA]
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197 |
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#set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVTTL} [get_ports SS3/OSD]
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198 |
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#set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVTTL} [get_ports SS4/SD_DIRECT]
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199 |
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200 |
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#
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201 |
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# SATA connectors
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202 |
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#
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203 |
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204 |
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#set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVTTL} [get_ports SATA1_RX_N]
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205 |
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#set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVTTL} [get_ports SATA1_RX_P]
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206 |
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#set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVTTL} [get_ports SATA1_TX_N]
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207 |
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#set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVTTL} [get_ports SATA1_TX_P]
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208 |
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#set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVTTL} [get_ports SATA2_RX_N]
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209 |
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#set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVTTL} [get_ports SATA2_RX_P]
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210 |
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#set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVTTL} [get_ports SATA2_TX_N]
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211 |
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#set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVTTL} [get_ports SATA2_TX_P]
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212 |
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213 |
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214 |
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#
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215 |
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# Other, never used, but ...
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216 |
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#
|
217 |
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218 |
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#set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVTTL} [get_ports VREF_DDR]
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219 |
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#set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVTTL} [get_ports VREF_DDR]
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220 |
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221 |
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#set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVTTL} [get_ports FPGA_TCK]
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222 |
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#set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVTTL} [get_ports FPGA_TDI]
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223 |
|
|
#set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVTTL} [get_ports FPGA_TDO]
|
224 |
|
|
#set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVTTL} [get_ports FPGA_TMS]
|
225 |
|
|
|
226 |
|
|
#set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVTTL} [get_ports FPGA_M0]
|
227 |
|
|
#set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVTTL} [get_ports FPGA_M1]
|
228 |
|
|
#set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVTTL} [get_ports FPGA_M2]
|
229 |
|
|
|
230 |
|
|
|
231 |
|
|
#
|
232 |
|
|
# DDR
|
233 |
|
|
#
|
234 |
|
|
|
235 |
|
|
|
236 |
|
|
set_property PACKAGE_PIN A1 [get_ports {DDR3ADDR[0]}]
|
237 |
|
|
set_property PACKAGE_PIN B2 [get_ports {DDR3ADDR[1]}]
|
238 |
|
|
set_property PACKAGE_PIN D2 [get_ports {DDR3ADDR[2]}]
|
239 |
|
|
set_property PACKAGE_PIN H3 [get_ports {DDR3ADDR[3]}]
|
240 |
|
|
set_property PACKAGE_PIN G2 [get_ports {DDR3ADDR[4]}]
|
241 |
|
|
set_property PACKAGE_PIN F3 [get_ports {DDR3ADDR[5]}]
|
242 |
|
|
set_property PACKAGE_PIN H2 [get_ports {DDR3ADDR[6]}]
|
243 |
|
|
set_property PACKAGE_PIN B1 [get_ports {DDR3ADDR[7]}]
|
244 |
|
|
set_property PACKAGE_PIN E1 [get_ports {DDR3ADDR[8]}]
|
245 |
|
|
set_property PACKAGE_PIN E2 [get_ports {DDR3ADDR[9]}]
|
246 |
|
|
set_property PACKAGE_PIN H5 [get_ports {DDR3ADDR[10]}]
|
247 |
|
|
set_property PACKAGE_PIN D1 [get_ports {DDR3ADDR[11]}]
|
248 |
|
|
set_property PACKAGE_PIN J5 [get_ports {DDR3ADDR[12]}]
|
249 |
|
|
set_property PACKAGE_PIN C2 [get_ports {DDR3ADDR[13]}]
|
250 |
|
|
|
251 |
|
|
set_property PACKAGE_PIN F1 [get_ports {DDR3BA[0]}]
|
252 |
|
|
set_property PACKAGE_PIN J2 [get_ports {DDR3BA[1]}]
|
253 |
|
|
set_property PACKAGE_PIN G1 [get_ports {DDR3BA[2]}]
|
254 |
|
|
|
255 |
|
|
set_property PACKAGE_PIN G4 [get_ports DDR3CAS_N]
|
256 |
|
|
|
257 |
|
|
set_property PACKAGE_PIN K2 [get_ports {DDR3CKE}]
|
258 |
|
|
set_property PACKAGE_PIN J1 [get_ports {DDR3CK_N}]
|
259 |
|
|
set_property PACKAGE_PIN K1 [get_ports {DDR3CK_P}]
|
260 |
|
|
|
261 |
|
|
set_property PACKAGE_PIN J6 [get_ports {DDR3DM[0]}]
|
262 |
|
|
set_property PACKAGE_PIN N4 [get_ports {DDR3DM[1]}]
|
263 |
|
|
|
264 |
|
|
set_property PACKAGE_PIN K6 [get_ports {DDR3DQ[0]}]
|
265 |
|
|
set_property PACKAGE_PIN L5 [get_ports {DDR3DQ[1]}]
|
266 |
|
|
set_property PACKAGE_PIN L3 [get_ports {DDR3DQ[2]}]
|
267 |
|
|
set_property PACKAGE_PIN L4 [get_ports {DDR3DQ[3]}]
|
268 |
|
|
set_property PACKAGE_PIN K4 [get_ports {DDR3DQ[4]}]
|
269 |
|
|
set_property PACKAGE_PIN M2 [get_ports {DDR3DQ[5]}]
|
270 |
|
|
set_property PACKAGE_PIN J4 [get_ports {DDR3DQ[6]}]
|
271 |
|
|
set_property PACKAGE_PIN K3 [get_ports {DDR3DQ[7]}]
|
272 |
|
|
|
273 |
|
|
set_property PACKAGE_PIN R1 [get_ports {DDR3DQ[8]}]
|
274 |
|
|
set_property PACKAGE_PIN N5 [get_ports {DDR3DQ[9]}]
|
275 |
|
|
set_property PACKAGE_PIN P1 [get_ports {DDR3DQ[10]}]
|
276 |
|
|
set_property PACKAGE_PIN P6 [get_ports {DDR3DQ[11]}]
|
277 |
|
|
set_property PACKAGE_PIN N2 [get_ports {DDR3DQ[12]}]
|
278 |
|
|
set_property PACKAGE_PIN P2 [get_ports {DDR3DQ[13]}]
|
279 |
|
|
set_property PACKAGE_PIN M5 [get_ports {DDR3DQ[14]}]
|
280 |
|
|
set_property PACKAGE_PIN M6 [get_ports {DDR3DQ[15]}]
|
281 |
|
|
|
282 |
|
|
set_property PACKAGE_PIN L1 [get_ports {DDR3DQS_N[0]}]
|
283 |
|
|
set_property PACKAGE_PIN P4 [get_ports {DDR3DQS_N[1]}]
|
284 |
|
|
set_property PACKAGE_PIN M1 [get_ports {DDR3DQS_P[0]}]
|
285 |
|
|
set_property PACKAGE_PIN P5 [get_ports {DDR3DQS_P[1]}]
|
286 |
|
|
set_property PACKAGE_PIN F4 [get_ports {DDR3ODT}]
|
287 |
|
|
set_property PACKAGE_PIN H4 [get_ports DDR3RAS_N]
|
288 |
|
|
set_property PACKAGE_PIN L6 [get_ports DDR3RST_N]
|
289 |
|
|
set_property PACKAGE_PIN G3 [get_ports DDR3WE_N]
|
290 |
|
|
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
#
|
294 |
|
|
# Other constraints ........................................................
|
295 |
|
|
#
|
296 |
|
|
|
297 |
|
|
create_clock -name {clk100} [get_ports {i_100MHz_P}] -period {10.000} -add
|
298 |
|
|
|
299 |
|
|
#eof
|