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[/] [v586/] [trunk/] [board_specific_files/] [esa11/] [rstgen.v] - Blame information for rev 121

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1 121 ultro
/*
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 * Copyright (c) 2015, Arch Labolatory
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * 1. Redistributions of source code must retain the above copyright notice,
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 *    this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
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 *    this list of conditions and the following disclaimer in the documentation
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 *    and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 *
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 */
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module RSTGEN(CLK, RST_X_I, RST_X_O);
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    input  CLK, RST_X_I;
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    output RST_X_O;
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    reg [7:0] cnt;
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    assign RST_X_O = cnt[7];
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    always @(posedge CLK or negedge RST_X_I) begin
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        if      (!RST_X_I) cnt <= 0;
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        else if (~RST_X_O) cnt <= (cnt + 1'b1);
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    end
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endmodule

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