1 |
121 |
ultro |
/* verilator lint_off UNUSED */
|
2 |
|
|
/* verilator lint_off CASEX */
|
3 |
|
|
/* verilator lint_off PINNOCONNECT */
|
4 |
|
|
/* verilator lint_off PINMISSING */
|
5 |
|
|
/* verilator lint_off IMPLICIT */
|
6 |
|
|
/* verilator lint_off WIDTH */
|
7 |
|
|
/* verilator lint_off UNDRIVEN */
|
8 |
|
|
|
9 |
|
|
// `define EMC
|
10 |
|
|
`define notEMC
|
11 |
|
|
|
12 |
|
|
module TOP_SYS(
|
13 |
|
|
clk100,
|
14 |
|
|
TXD,rstn,gpio_in,RXD,
|
15 |
|
|
extA,extDB,extWEN,extUB,extLB,extCSN,extWAIT,
|
16 |
|
|
extOE,extCLK,extADV,extCRE,
|
17 |
|
|
sdin,sdout,sdwp,sdhld,sdcs,
|
18 |
|
|
gpioA,gpioB
|
19 |
|
|
);
|
20 |
|
|
|
21 |
|
|
input clk100;
|
22 |
|
|
input rstn;
|
23 |
|
|
output TXD;
|
24 |
|
|
input [6:0] gpio_in;
|
25 |
|
|
output extCLK,extCRE;
|
26 |
|
|
output extADV,extUB,extLB,extWEN,extCSN,extOE;
|
27 |
|
|
input RXD;
|
28 |
|
|
output sdout,sdwp,sdhld,sdcs;
|
29 |
|
|
input sdin;
|
30 |
|
|
inout [7:0] gpioA,gpioB;
|
31 |
|
|
input extWAIT;
|
32 |
|
|
|
33 |
|
|
|
34 |
|
|
// external mem I/F
|
35 |
|
|
inout [15:0] extDB;
|
36 |
|
|
output [23:0] extA;
|
37 |
|
|
|
38 |
|
|
// axi bus
|
39 |
|
|
wire [31:0] M_AXI_AW, M_AXI_AR;
|
40 |
|
|
wire M_AXI_AWVALID,M_AXI_ARVALID,M_AXI_WVALID,M_AXI_RREADY;
|
41 |
|
|
wire M_AXI_AWREADY,M_AXI_ARREADY,M_AXI_WREADY,M_AXI_RVALID,M_AXI_RLAST,M_AXI_WLAST;
|
42 |
|
|
wire [31:0] M_AXI_R;
|
43 |
|
|
wire [31:0] M_AXI_W;
|
44 |
|
|
wire [3:0] M_AXI_WSTRB;
|
45 |
|
|
wire [1:0] M_AXI_ARBURST;
|
46 |
|
|
wire [3:0] M_AXI_ARLEN;
|
47 |
|
|
wire [2:0] M_AXI_ARSIZE;
|
48 |
|
|
wire [1:0] M_AXI_AWBURST;
|
49 |
|
|
wire [3:0] M_AXI_AWLEN;
|
50 |
|
|
wire [2:0] M_AXI_AWSIZE;
|
51 |
|
|
|
52 |
|
|
wire [15:0] extDBo,extDBt;
|
53 |
|
|
|
54 |
|
|
wire [7:0] gpioA_dir,gpioB_dir,gpioA_out,gpioB_out;
|
55 |
|
|
wire [31:0] romA,romQ;
|
56 |
|
|
|
57 |
|
|
// axi arbiter
|
58 |
|
|
wire M_AXI_ARREADY_ram , M_AXI_ARREADY_rom;
|
59 |
|
|
wire M_AXI_RVALID_ram , M_AXI_RVALID_rom;
|
60 |
|
|
wire M_AXI_RLAST_ram , M_AXI_RLAST_rom;
|
61 |
|
|
wire [31:0] M_AXI_R_ram , M_AXI_R_rom;
|
62 |
|
|
wire M_AXI_ARVALID_rom = (M_AXI_AR[31:12] == 20'h000ff) ? M_AXI_ARVALID :0;
|
63 |
|
|
wire M_AXI_ARVALID_ram = (M_AXI_AR[31:12] != 20'h000ff) ? M_AXI_ARVALID :0;
|
64 |
|
|
wire [3:0] M_AXI_ARLEN_ram = (M_AXI_AR[31:12] != 20'h000ff) ? M_AXI_ARLEN :0;
|
65 |
|
|
|
66 |
|
|
assign M_AXI_ARREADY = M_AXI_ARREADY_ram | M_AXI_ARREADY_rom;
|
67 |
|
|
assign M_AXI_RVALID = M_AXI_RVALID_ram | M_AXI_RVALID_rom;
|
68 |
|
|
assign M_AXI_RLAST = M_AXI_RLAST_ram | M_AXI_RLAST_rom;
|
69 |
|
|
assign M_AXI_R = (M_AXI_RVALID_ram) ? M_AXI_R_ram : M_AXI_R_rom;
|
70 |
|
|
|
71 |
|
|
wire clk;
|
72 |
|
|
|
73 |
|
|
clk_wiz_v3_6 clk_wiz_v3_6 (.CLK_IN1(clk100) , .CLK_OUT1(clk) );
|
74 |
|
|
|
75 |
|
|
STARTUPE2 #(
|
76 |
|
|
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
|
77 |
|
|
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
|
78 |
|
|
)
|
79 |
|
|
STARTUPE2_inst (
|
80 |
|
|
.CFGCLK(), // 1-bit output: Configuration main clock output
|
81 |
|
|
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
|
82 |
|
|
.EOS(), // 1-bit output: Active high output signal indicating the End Of Startup.
|
83 |
|
|
.PREQ(), // 1-bit output: PROGRAM request to fabric output
|
84 |
|
|
.CLK(1'b0), // 1-bit input: User start-up clock input
|
85 |
|
|
.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
|
86 |
|
|
.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
|
87 |
|
|
.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
|
88 |
|
|
.PACK(1'b0), // 1-bit input: PROGRAM acknowledge input
|
89 |
|
|
.USRCCLKO(sdclk), // 1-bit input: User CCLK input
|
90 |
|
|
.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
|
91 |
|
|
.USRDONEO(1'b1), // 1-bit input: User DONE pin output control
|
92 |
|
|
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
|
93 |
|
|
);
|
94 |
|
|
|
95 |
|
|
v586 v586 (
|
96 |
|
|
.m00_AXI_RSTN(rstn),.m00_AXI_CLK(clk),.cfg(gpio_in[6:0]),
|
97 |
|
|
// spi
|
98 |
|
|
.spi_mosi(sdout),
|
99 |
|
|
.spi_miso(sdin),
|
100 |
|
|
.spi_clk(sdclk),
|
101 |
|
|
.spi_cs(sdcs),
|
102 |
|
|
// axi interface 32bit
|
103 |
|
|
.m00_AXI_AWADDR(M_AXI_AW), .m00_AXI_AWVALID(M_AXI_AWVALID), .m00_AXI_AWREADY(M_AXI_AWREADY),
|
104 |
|
|
.m00_AXI_AWBURST(M_AXI_AWBURST), .m00_AXI_AWLEN(M_AXI_AWLEN), .m00_AXI_AWSIZE(M_AXI_AWSIZE),
|
105 |
|
|
.m00_AXI_WDATA(M_AXI_W), .m00_AXI_WVALID(M_AXI_WVALID), .m00_AXI_WREADY(M_AXI_WREADY), .m00_AXI_WSTRB(M_AXI_WSTRB), .m00_AXI_WLAST(M_AXI_WLAST),
|
106 |
|
|
.m00_AXI_ARADDR(M_AXI_AR), .m00_AXI_ARVALID(M_AXI_ARVALID), .m00_AXI_ARREADY(M_AXI_ARREADY),
|
107 |
|
|
.m00_AXI_ARBURST(M_AXI_ARBURST), .m00_AXI_ARLEN(M_AXI_ARLEN), .m00_AXI_ARSIZE(M_AXI_ARSIZE),
|
108 |
|
|
.m00_AXI_RDATA(M_AXI_R), .m00_AXI_RVALID(M_AXI_RVALID), .m00_AXI_RREADY(M_AXI_RREADY), .m00_AXI_RLAST(M_AXI_RLAST),
|
109 |
|
|
.m00_AXI_BVALID(1'b1),.m00_AXI_BREADY(m00_AXI_BREADY),
|
110 |
|
|
// interrupts
|
111 |
|
|
.int1(1'b0),.int2(1'b0),.int3(1'b0),.int5(1'b0),.int6(1'b0),.int7(1'b0),
|
112 |
|
|
// gpio
|
113 |
|
|
.gpioA_in(gpioA),.gpioB_in(gpioB),
|
114 |
|
|
.gpioA_out(gpioA_out),.gpioB_out(gpioB_out),
|
115 |
|
|
.gpioA_dir(gpioA_dir),.gpioB_dir(gpioB_dir),
|
116 |
|
|
//uart
|
117 |
|
|
.RXD(RXD),
|
118 |
|
|
.TXD(TXD)
|
119 |
|
|
);
|
120 |
|
|
|
121 |
|
|
assign sdwp = 1'b1;
|
122 |
|
|
assign sdhld = 1'b1;
|
123 |
|
|
//
|
124 |
|
|
// MEMORY CONTROL : Internal ROM/External RAM arbitration
|
125 |
|
|
// External RAM State Machine REQ/ACK/busrt on whishbone bus
|
126 |
|
|
|
127 |
|
|
`ifdef notEMC
|
128 |
|
|
psram_axi psram_axi(
|
129 |
|
|
// MEM
|
130 |
|
|
.MEM_ADDR_OUT(extA[23:1]),
|
131 |
|
|
.MEM_CEN(extCSN),
|
132 |
|
|
.MEM_OEN(extOE),
|
133 |
|
|
.MEM_WEN(extWEN),
|
134 |
|
|
.MEM_BEN({extUB,extLB}),
|
135 |
|
|
.MEM_ADV(extADV),
|
136 |
|
|
.MEM_CRE(extCRE),
|
137 |
|
|
.MEM_DATA_I(extDB),
|
138 |
|
|
.MEM_DATA_O(extDBo),
|
139 |
|
|
.MEM_DATA_T(extDBt),
|
140 |
|
|
// CTRL
|
141 |
|
|
.s00_axi_aclk(clk),
|
142 |
|
|
.s00_axi_aresetn(rstn),
|
143 |
|
|
// AXI
|
144 |
|
|
// AW CHANNEL
|
145 |
|
|
.s00_axi_awid(2'b00),
|
146 |
|
|
.s00_axi_awaddr(M_AXI_AW[23:0]),
|
147 |
|
|
.s00_axi_awlen({4'h0,M_AXI_AWLEN}),
|
148 |
|
|
.s00_axi_awsize(M_AXI_AWSIZE),
|
149 |
|
|
.s00_axi_awburst(M_AXI_AWBURST),
|
150 |
|
|
.s00_axi_awlock(1'b0),
|
151 |
|
|
.s00_axi_awcache(4'h0),
|
152 |
|
|
.s00_axi_awprot(3'h0),
|
153 |
|
|
.s00_axi_awqos(4'h0),
|
154 |
|
|
.s00_axi_awregion(4'h0),
|
155 |
|
|
.s00_axi_awuser(2'h0),
|
156 |
|
|
.s00_axi_awvalid(M_AXI_AWVALID),
|
157 |
|
|
.s00_axi_awready(M_AXI_AWREADY),
|
158 |
|
|
// W CHANNEL
|
159 |
|
|
.s00_axi_wdata(M_AXI_W),
|
160 |
|
|
.s00_axi_wstrb(M_AXI_WSTRB),
|
161 |
|
|
.s00_axi_wlast(M_AXI_WLAST),
|
162 |
|
|
.s00_axi_wuser(2'b0),
|
163 |
|
|
.s00_axi_wvalid(M_AXI_WVALID),
|
164 |
|
|
.s00_axi_wready(M_AXI_WREADY),
|
165 |
|
|
// B CHANNEL
|
166 |
|
|
.s00_axi_bid(),
|
167 |
|
|
.s00_axi_bresp(),
|
168 |
|
|
.s00_axi_buser(),
|
169 |
|
|
.s00_axi_bvalid(),
|
170 |
|
|
.s00_axi_bready(1'b1),
|
171 |
|
|
// AR CHANNEL
|
172 |
|
|
.s00_axi_arid(2'b0),
|
173 |
|
|
.s00_axi_araddr(M_AXI_AR[23:0]),
|
174 |
|
|
.s00_axi_arlen({4'b0,M_AXI_ARLEN}),
|
175 |
|
|
.s00_axi_arsize(M_AXI_ARSIZE),
|
176 |
|
|
.s00_axi_arburst(M_AXI_ARBURST),
|
177 |
|
|
.s00_axi_arlock(1'b0),
|
178 |
|
|
.s00_axi_arcache(4'h0),
|
179 |
|
|
.s00_axi_arprot(3'h0),
|
180 |
|
|
.s00_axi_arqos(4'h0),
|
181 |
|
|
.s00_axi_arregion(4'h0),
|
182 |
|
|
.s00_axi_aruser(2'h0),
|
183 |
|
|
.s00_axi_arvalid(M_AXI_ARVALID_ram),
|
184 |
|
|
.s00_axi_arready(M_AXI_ARREADY_ram),
|
185 |
|
|
// R CHANNEL
|
186 |
|
|
.s00_axi_rid(),
|
187 |
|
|
.s00_axi_rdata(M_AXI_R_ram),
|
188 |
|
|
.s00_axi_rresp(),
|
189 |
|
|
.s00_axi_rlast(M_AXI_RLAST_ram),
|
190 |
|
|
.s00_axi_ruser(),
|
191 |
|
|
.s00_axi_rvalid(M_AXI_RVALID_ram),
|
192 |
|
|
.s00_axi_rready(M_AXI_RREADY)
|
193 |
|
|
);
|
194 |
|
|
|
195 |
|
|
assign extCLK = 0;
|
196 |
|
|
`endif
|
197 |
|
|
|
198 |
|
|
`ifdef EMC
|
199 |
|
|
wire [31:0] extA_i;
|
200 |
|
|
wire extCKEN;
|
201 |
|
|
|
202 |
|
|
axi_emc_0 axi_emc_0 (
|
203 |
|
|
.s_axi_aclk(clk),
|
204 |
|
|
.s_axi_aresetn(rstn),
|
205 |
|
|
.rdclk(clk),
|
206 |
|
|
.s_axi_mem_awid (4'h0),
|
207 |
|
|
.s_axi_mem_awaddr({8'b0,M_AXI_AW[23:0]}),
|
208 |
|
|
.s_axi_mem_awlen({4'h0,M_AXI_AWLEN}),
|
209 |
|
|
.s_axi_mem_awsize(M_AXI_AWSIZE),
|
210 |
|
|
.s_axi_mem_awburst(M_AXI_AWBURST),
|
211 |
|
|
.s_axi_mem_awlock(1'b0),
|
212 |
|
|
.s_axi_mem_awcache(4'h0),
|
213 |
|
|
.s_axi_mem_awprot(3'h0),
|
214 |
|
|
.s_axi_mem_awvalid(M_AXI_AWVALID),
|
215 |
|
|
.s_axi_mem_awready(M_AXI_AWREADY),
|
216 |
|
|
.s_axi_mem_wdata(M_AXI_W),
|
217 |
|
|
.s_axi_mem_wstrb(M_AXI_WSTRB),
|
218 |
|
|
.s_axi_mem_wlast(M_AXI_WLAST),
|
219 |
|
|
.s_axi_mem_wvalid(M_AXI_WVALID),
|
220 |
|
|
.s_axi_mem_wready(M_AXI_WREADY),
|
221 |
|
|
.s_axi_mem_bid(),
|
222 |
|
|
.s_axi_mem_bresp(),
|
223 |
|
|
.s_axi_mem_bvalid(),
|
224 |
|
|
.s_axi_mem_bready(m00_AXI_BREADY),
|
225 |
|
|
.s_axi_mem_arid(4'h0),
|
226 |
|
|
.s_axi_mem_araddr({8'b0,M_AXI_AR[23:0]}),
|
227 |
|
|
.s_axi_mem_arlen({4'b0,M_AXI_ARLEN_ram}),
|
228 |
|
|
.s_axi_mem_arsize(M_AXI_ARSIZE),
|
229 |
|
|
.s_axi_mem_arburst(M_AXI_ARBURST),
|
230 |
|
|
.s_axi_mem_arlock(1'b0),
|
231 |
|
|
.s_axi_mem_arcache(4'h0),
|
232 |
|
|
.s_axi_mem_arprot(3'h0),
|
233 |
|
|
.s_axi_mem_arvalid(M_AXI_ARVALID_ram),
|
234 |
|
|
.s_axi_mem_arready(M_AXI_ARREADY_ram),
|
235 |
|
|
.s_axi_mem_rid(),
|
236 |
|
|
.s_axi_mem_rdata(M_AXI_R_ram),
|
237 |
|
|
.s_axi_mem_rresp(),
|
238 |
|
|
.s_axi_mem_rlast(M_AXI_RLAST_ram),
|
239 |
|
|
.s_axi_mem_rvalid(M_AXI_RVALID_ram),
|
240 |
|
|
.s_axi_mem_rready(M_AXI_RREADY),
|
241 |
|
|
.mem_dq_i(extDB),
|
242 |
|
|
.mem_dq_o(extDBo),
|
243 |
|
|
.mem_dq_t(extDBt),
|
244 |
|
|
.mem_a(extA_i),
|
245 |
|
|
.mem_ce(),
|
246 |
|
|
.mem_cen(extCSN),
|
247 |
|
|
.mem_oen(extOE),
|
248 |
|
|
.mem_wen(extWEN),
|
249 |
|
|
.mem_ben({extUB,extLB}),
|
250 |
|
|
.mem_qwen(),
|
251 |
|
|
.mem_rpn(),
|
252 |
|
|
.mem_adv_ldn(extADV),
|
253 |
|
|
.mem_lbon(),
|
254 |
|
|
.mem_cken(extCKEN),
|
255 |
|
|
.mem_rnw(),
|
256 |
|
|
.mem_cre(),
|
257 |
|
|
.mem_wait(extWAIT)
|
258 |
|
|
);
|
259 |
|
|
|
260 |
|
|
assign extCRE = 1'b0;
|
261 |
|
|
assign extA[23:1] = extA_i[23:1];
|
262 |
|
|
assign extCLK = extCKEN & clk;
|
263 |
|
|
`endif
|
264 |
|
|
|
265 |
|
|
assign extDB = extOE ? extDBo : 32'bz ;
|
266 |
|
|
|
267 |
|
|
axi_rom bootrom (
|
268 |
|
|
.clk(clk),
|
269 |
|
|
.rstn(rstn),
|
270 |
|
|
.axi_ARVALID(M_AXI_ARVALID_rom),
|
271 |
|
|
.axi_ARREADY(M_AXI_ARREADY_rom),
|
272 |
|
|
.axi_AR(M_AXI_AR),
|
273 |
|
|
.axi_ARBURST(M_AXI_ARBURST),
|
274 |
|
|
.axi_ARLEN(M_AXI_ARLEN),
|
275 |
|
|
.axi_RLAST(M_AXI_RLAST_rom),
|
276 |
|
|
.axi_R(M_AXI_R_rom),
|
277 |
|
|
.axi_RVALID(M_AXI_RVALID_rom),
|
278 |
|
|
.axi_RREADY(M_AXI_RREADY)
|
279 |
|
|
);
|
280 |
|
|
|
281 |
|
|
assign gpioA[0] = (gpioA_dir[0] == 0) ? 1'bz : gpioA_out[0];
|
282 |
|
|
assign gpioA[1] = (gpioA_dir[1] == 0) ? 1'bz : gpioA_out[1];
|
283 |
|
|
assign gpioA[2] = (gpioA_dir[2] == 0) ? 1'bz : gpioA_out[2];
|
284 |
|
|
assign gpioA[3] = (gpioA_dir[3] == 0) ? 1'bz : gpioA_out[3];
|
285 |
|
|
assign gpioA[4] = (gpioA_dir[4] == 0) ? 1'bz : gpioA_out[4];
|
286 |
|
|
assign gpioA[5] = (gpioA_dir[5] == 0) ? 1'bz : gpioA_out[5];
|
287 |
|
|
assign gpioA[6] = (gpioA_dir[6] == 0) ? 1'bz : gpioA_out[6];
|
288 |
|
|
assign gpioA[7] = (gpioA_dir[7] == 0) ? 1'bz : gpioA_out[7];
|
289 |
|
|
assign gpioB[0] = (gpioB_dir[0] == 0) ? 1'bz : gpioB_out[0];
|
290 |
|
|
assign gpioB[1] = (gpioB_dir[1] == 0) ? 1'bz : gpioB_out[1];
|
291 |
|
|
assign gpioB[2] = (gpioB_dir[2] == 0) ? 1'bz : gpioB_out[2];
|
292 |
|
|
assign gpioB[3] = (gpioB_dir[3] == 0) ? 1'bz : gpioB_out[3];
|
293 |
|
|
assign gpioB[4] = (gpioB_dir[4] == 0) ? 1'bz : gpioB_out[4];
|
294 |
|
|
assign gpioB[5] = (gpioB_dir[5] == 0) ? 1'bz : gpioB_out[5];
|
295 |
|
|
assign gpioB[6] = (gpioB_dir[6] == 0) ? 1'bz : gpioB_out[6];
|
296 |
|
|
assign gpioB[7] = (gpioB_dir[7] == 0) ? 1'bz : gpioB_out[7];
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
endmodule
|