1 |
121 |
ultro |
`define simu
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//
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module TOP_SYS(
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clk100,rstn,
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// uart
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TXD,RXD,
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// DDR2
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DDR2DQ,
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DDR2DQS_N,
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DDR2DQS_P,
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DDR2ADDR,
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DDR2BA,
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DDR2RAS_N,
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DDR2CAS_N,
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DDR2WE_N,
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DDR2CK_P,
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DDR2CK_N,
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DDR2CKE,
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DDR2CS_N,
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DDR2DM,
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DDR2ODT,
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// spi flash
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sdin,sdout,sdwp,sdhld,sdcs,sdreset,
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// gpio it87xx
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gpioA,gpioB,
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// ethernet
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PhyMdc,
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PhyMdio,
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PhyRstn,
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PhyCrs,
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PhyRxErr,
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PhyRxd,
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PhyTxEn,
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PhyTxd,
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PhyClk50Mhz,
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// tiny spi
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miso,
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mosi,
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sclk,
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aclInt1,
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aclInt2,
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debug
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);
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input clk100;
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input rstn;
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output TXD;
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wire [6:0] gpio_in;
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inout wire [15:0] DDR2DQ;
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inout wire [1:0] DDR2DQS_N;
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inout wire [1:0] DDR2DQS_P;
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output wire [12:0] DDR2ADDR;
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output wire [2:0] DDR2BA;
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output wire DDR2RAS_N;
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output wire DDR2CAS_N;
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output wire DDR2WE_N;
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output wire DDR2CK_P;
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output wire DDR2CK_N;
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output wire DDR2CKE;
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output wire DDR2CS_N;
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output wire [1:0] DDR2DM;
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output wire DDR2ODT;
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input RXD;
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output sdout,sdwp,sdhld,sdcs;
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input sdin;
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inout [7:0] gpioA,gpioB;
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//input extWAIT;
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output reg sdreset;
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// tiny spi
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output mosi;
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input miso;
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output sclk;
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input aclInt1,aclInt2;
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// ethernet
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output PhyMdc;
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inout PhyMdio;
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wire PhyMdio_t;
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wire PhyMdio_o;
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wire PhyMdio_i;
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wire int_net;
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output PhyRstn;
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output PhyCrs;
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input PhyRxErr;
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input [1:0] PhyRxd;
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output PhyTxEn;
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output [1:0] PhyTxd;
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output reg PhyClk50Mhz;
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output reg [3:0] debug;
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wire [4:0] debug_int;
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wire rmii2mac_tx_clk;
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wire rmii2mac_rx_clk;
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wire rmii2mac_crs;
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wire rmii2mac_rx_dv;
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wire [3:0] rmii2mac_rxd;
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wire rmii2mac_col;
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wire rmii2mac_rx_er;
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wire mac2rmii_tx_en;
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wire [3:0] mac2rmii_txd;
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wire mac2rmii_tx_er;
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// axi cpu bus
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wire [31:0] M_AXI_AW, M_AXI_AR;
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wire M_AXI_AWVALID,M_AXI_ARVALID,M_AXI_WVALID,M_AXI_RREADY;
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wire M_AXI_AWREADY,M_AXI_ARREADY,M_AXI_WREADY,M_AXI_RVALID,M_AXI_RLAST,M_AXI_WLAST;
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wire [31:0] M_AXI_R;
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wire [31:0] M_AXI_W;
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wire [3:0] M_AXI_WSTRB;
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wire [1:0] M_AXI_ARBURST;
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wire [7:0] M_AXI_ARLEN;
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wire [2:0] M_AXI_ARSIZE;
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wire [1:0] M_AXI_AWBURST;
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wire [7:0] M_AXI_AWLEN;
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wire [2:0] M_AXI_AWSIZE;
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// axi ram bus
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wire [31:0] S_AXI_AW_ram, S_AXI_AR_ram;
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wire S_AXI_AWVALID_ram,S_AXI_ARVALID_ram,S_AXI_WVALID_ram,S_AXI_RREADY_ram;
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wire S_AXI_AWREADY_ram,S_AXI_ARREADY_ram,S_AXI_WREADY_ram,S_AXI_RVALID_ram,S_AXI_RLAST_ram,S_AXI_WLAST_ram;
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wire [31:0] S_AXI_R_ram;
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wire [31:0] S_AXI_W_ram;
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wire [3:0] S_AXI_WSTRB_ram;
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wire [1:0] S_AXI_ARBURST_ram;
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wire [7:0] S_AXI_ARLEN_ram;
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wire [2:0] S_AXI_ARSIZE_ram;
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wire [1:0] S_AXI_AWBURST_ram;
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wire [7:0] S_AXI_AWLEN_ram;
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wire [2:0] S_AXI_AWSIZE_ram;
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// axi rom bus
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wire [31:0] S_AXI_AW_rom, S_AXI_AR_rom;
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wire S_AXI_AWVALID_rom,S_AXI_ARVALID_rom,S_AXI_WVALID_rom,S_AXI_RREADY_rom;
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wire S_AXI_AWREADY_rom,S_AXI_ARREADY_rom,S_AXI_WREADY_rom,S_AXI_RVALID_rom,S_AXI_RLAST_rom,S_AXI_WLAST_rom;
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wire [31:0] S_AXI_R_rom;
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wire [31:0] S_AXI_W_rom;
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wire [3:0] S_AXI_WSTRB_rom;
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wire [1:0] S_AXI_ARBURST_rom;
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wire [7:0] S_AXI_ARLEN_rom;
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wire [2:0] S_AXI_ARSIZE_rom;
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wire [1:0] S_AXI_AWBURST_rom;
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wire [7:0] S_AXI_AWLEN_rom;
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wire [2:0] S_AXI_AWSIZE_rom;
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// axi net bus
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wire [31:0] S_AXI_AW_net, S_AXI_AR_net;
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wire S_AXI_AWVALID_net,S_AXI_ARVALID_net,S_AXI_WVALID_net,S_AXI_RREADY_net;
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wire S_AXI_AWREADY_net,S_AXI_ARREADY_net,S_AXI_WREADY_net,S_AXI_RVALID_net,S_AXI_RLAST_net,S_AXI_WLAST_net;
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wire [31:0] S_AXI_R_net;
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wire [31:0] S_AXI_W_net;
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wire [3:0] S_AXI_WSTRB_net;
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wire [1:0] S_AXI_ARBURST_net;
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wire [7:0] S_AXI_ARLEN_net;
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wire [2:0] S_AXI_ARSIZE_net;
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wire [1:0] S_AXI_AWBURST_net;
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wire [7:0] S_AXI_AWLEN_net;
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wire [2:0] S_AXI_AWSIZE_net;
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// axi io bus
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wire [31:0] M_IO_AXI_AW, M_IO_AXI_AR;
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wire M_IO_AXI_AWVALID,M_IO_AXI_ARVALID,M_IO_AXI_WVALID,M_IO_AXI_RREADY;
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wire M_IO_AXI_AWREADY,M_IO_AXI_ARREADY,M_IO_AXI_WREADY,M_IO_AXI_RVALID,M_IO_AXI_RLAST,M_IO_AXI_WLAST;
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wire [31:0] M_IO_AXI_R;
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wire [31:0] M_IO_AXI_W;
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wire [3:0] M_IO_AXI_WSTRB;
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wire [1:0] M_IO_AXI_ARBURST;
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wire [3:0] M_IO_AXI_ARLEN;
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wire [2:0] M_IO_AXI_ARSIZE;
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wire [1:0] M_IO_AXI_AWBURST;
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wire [7:0] M_IO_AXI_AWLEN;
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wire [2:0] M_IO_AXI_AWSIZE;
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wire [15:0] extDBo,extDBt;
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wire [7:0] gpioA_dir,gpioB_dir,gpioA_out,gpioB_out;
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wire [31:0] romA,romQ;
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wire int_pic,iack;
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wire [7:0] ivect;
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wire clk;
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wire clk200;
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wire dram_rst_out;
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wire ui_clk_sync_rst;
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wire init_calib_complete;
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wire rstn_ddr;
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wire locked;
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assign gpio_in = 0;
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clk_wiz_0 i_clk_wiz_0
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(.clk_in1(clk100),
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.clk_out1(),
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.clk_out2(),
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.clk_out3(clk200),
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.locked(locked)
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);
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always @(posedge clk200) debug <= debug_int[3:0];
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RSTGEN rstgen(.CLK(clk200), .RST_X_I(~(~rstn | dram_rst_out)), .RST_X_O(rstn_ddr));
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assign dram_rst_out = (ui_clk_sync_rst | ~init_calib_complete);
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STARTUPE2 #(
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.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
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.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
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)
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STARTUPE2_inst (
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.CFGCLK(), // 1-bit output: Configuration main clock output
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.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
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.EOS(), // 1-bit output: Active high output signal indicating the End Of Startup.
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.PREQ(), // 1-bit output: PROGRAM request to fabric output
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.CLK(1'b0), // 1-bit input: User start-up clock input
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.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
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.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
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.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
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.PACK(1'b0), // 1-bit input: PROGRAM acknowledge input
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.USRCCLKO(sdclk), // 1-bit input: User CCLK input
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.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
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.USRDONEO(1'b1), // 1-bit input: User DONE pin output control
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.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
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);
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v586 v586 (
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.m00_AXI_RSTN(rstn_ddr),.m00_AXI_CLK(clk),
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// axi interface 32bit
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.m00_AXI_AWADDR(M_AXI_AW), .m00_AXI_AWVALID(M_AXI_AWVALID), .m00_AXI_AWREADY(M_AXI_AWREADY),
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.m00_AXI_AWBURST(M_AXI_AWBURST), .m00_AXI_AWLEN(M_AXI_AWLEN), .m00_AXI_AWSIZE(M_AXI_AWSIZE),
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.m00_AXI_WDATA(M_AXI_W), .m00_AXI_WVALID(M_AXI_WVALID), .m00_AXI_WREADY(M_AXI_WREADY), .m00_AXI_WSTRB(M_AXI_WSTRB), .m00_AXI_WLAST(M_AXI_WLAST),
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235 |
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.m00_AXI_ARADDR(M_AXI_AR), .m00_AXI_ARVALID(M_AXI_ARVALID), .m00_AXI_ARREADY(M_AXI_ARREADY),
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.m00_AXI_ARBURST(M_AXI_ARBURST), .m00_AXI_ARLEN(M_AXI_ARLEN), .m00_AXI_ARSIZE(M_AXI_ARSIZE),
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237 |
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.m00_AXI_RDATA(M_AXI_R), .m00_AXI_RVALID(M_AXI_RVALID), .m00_AXI_RREADY(M_AXI_RREADY), .m00_AXI_RLAST(M_AXI_RLAST),
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.m00_AXI_BVALID(1'b1),.m00_AXI_BREADY(M_AXI_BREADY),
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239 |
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// axi io interface 32bit
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240 |
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.m01_AXI_AWADDR(M_IO_AXI_AW), .m01_AXI_AWVALID(M_IO_AXI_AWVALID), .m01_AXI_AWREADY(M_IO_AXI_AWREADY),
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241 |
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.m01_AXI_AWBURST(M_IO_AXI_AWBURST), .m01_AXI_AWLEN(M_IO_AXI_AWLEN), .m01_AXI_AWSIZE(M_IO_AXI_AWSIZE),
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242 |
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.m01_AXI_WDATA(M_IO_AXI_W), .m01_AXI_WVALID(M_IO_AXI_WVALID), .m01_AXI_WREADY(M_IO_AXI_WREADY), .m01_AXI_WSTRB(M_IO_AXI_WSTRB), .m01_AXI_WLAST(M_IO_AXI_WLAST),
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243 |
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.m01_AXI_ARADDR(M_IO_AXI_AR), .m01_AXI_ARVALID(M_IO_AXI_ARVALID), .m01_AXI_ARREADY(M_IO_AXI_ARREADY),
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244 |
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.m01_AXI_ARBURST(M_IO_AXI_ARBURST), .m01_AXI_ARLEN(M_IO_AXI_ARLEN), .m01_AXI_ARSIZE(M_IO_AXI_ARSIZE),
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245 |
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.m01_AXI_RDATA(M_IO_AXI_R), .m01_AXI_RVALID(M_IO_AXI_RVALID), .m01_AXI_RREADY(M_IO_AXI_RREADY), .m01_AXI_RLAST(M_IO_AXI_RLAST),
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246 |
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.m01_AXI_BVALID(1'b1),.m01_AXI_BREADY(M_IO_AXI_BREADY),
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247 |
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// interrupts
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248 |
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.int_pic(int_pic),.ivect(ivect),.iack(iack), .debug(debug_int)
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249 |
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);
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250 |
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251 |
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252 |
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ddr_axi i_ddr_axi (
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253 |
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// Inouts
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254 |
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.ddr2_dq(DDR2DQ),
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255 |
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.ddr2_dqs_n(DDR2DQS_N),
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256 |
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.ddr2_dqs_p(DDR2DQS_P),
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257 |
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// Outputs
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258 |
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.ddr2_addr(DDR2ADDR),
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259 |
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.ddr2_ba(DDR2BA),
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260 |
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.ddr2_ras_n(DDR2RAS_N),
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261 |
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.ddr2_cas_n(DDR2CAS_N),
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262 |
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.ddr2_we_n(DDR2WE_N),
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263 |
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.ddr2_ck_p(DDR2CK_P),
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264 |
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.ddr2_ck_n(DDR2CK_N),
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265 |
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.ddr2_cke(DDR2CKE),
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266 |
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.ddr2_cs_n(DDR2CS_N),
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267 |
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.ddr2_dm(DDR2DM),
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268 |
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.ddr2_odt(DDR2ODT),
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269 |
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270 |
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// Inputs
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271 |
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// Single-ended system clock
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272 |
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.sys_clk_i(clk200),
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273 |
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// Single-ended iodelayctrl clk (reference clock)
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274 |
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.clk_ref_i(clk200),
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275 |
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// user interface signals
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276 |
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.ui_clk(clk),
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277 |
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.ui_clk_sync_rst(ui_clk_sync_rst),
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278 |
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.mmcm_locked(),
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279 |
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.aresetn(rstn),
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280 |
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.app_sr_req(0),
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281 |
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.app_ref_req(0),
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282 |
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.app_zq_req(0),
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283 |
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.app_sr_active(),
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284 |
|
|
.app_ref_ack(),
|
285 |
|
|
.app_zq_ack(),
|
286 |
|
|
// AXI
|
287 |
|
|
// AW CHANNEL
|
288 |
|
|
.s_axi_awid(4'b00),
|
289 |
|
|
.s_axi_awaddr(S_AXI_AW_ram),
|
290 |
|
|
.s_axi_awlen(S_AXI_AWLEN_ram),
|
291 |
|
|
.s_axi_awsize(S_AXI_AWSIZE_ram),
|
292 |
|
|
.s_axi_awburst(S_AXI_AWBURST_ram),
|
293 |
|
|
.s_axi_awlock(1'b0),
|
294 |
|
|
.s_axi_awcache(4'h0),
|
295 |
|
|
.s_axi_awprot(3'h0),
|
296 |
|
|
.s_axi_awqos(4'h0),
|
297 |
|
|
.s_axi_awvalid(S_AXI_AWVALID_ram),
|
298 |
|
|
.s_axi_awready(S_AXI_AWREADY_ram),
|
299 |
|
|
// W CHANNEL
|
300 |
|
|
.s_axi_wdata(S_AXI_W_ram),
|
301 |
|
|
.s_axi_wstrb(S_AXI_WSTRB_ram),
|
302 |
|
|
.s_axi_wlast(S_AXI_WLAST_ram),
|
303 |
|
|
.s_axi_wvalid(S_AXI_WVALID_ram),
|
304 |
|
|
.s_axi_wready(S_AXI_WREADY_ram),
|
305 |
|
|
// B CHANNEL
|
306 |
|
|
.s_axi_bid(),
|
307 |
|
|
.s_axi_bresp(),
|
308 |
|
|
.s_axi_bvalid(),
|
309 |
|
|
.s_axi_bready(1'b1),
|
310 |
|
|
// AR CHANNEL
|
311 |
|
|
.s_axi_arid(4'b0),
|
312 |
|
|
.s_axi_araddr(S_AXI_AR_ram),
|
313 |
|
|
.s_axi_arlen(S_AXI_ARLEN_ram),
|
314 |
|
|
.s_axi_arsize(S_AXI_ARSIZE_ram),
|
315 |
|
|
.s_axi_arburst(S_AXI_ARBURST_ram),
|
316 |
|
|
.s_axi_arlock(1'b0),
|
317 |
|
|
.s_axi_arcache(4'h0),
|
318 |
|
|
.s_axi_arprot(3'h0),
|
319 |
|
|
.s_axi_arqos(4'h0),
|
320 |
|
|
.s_axi_arvalid(S_AXI_ARVALID_ram),
|
321 |
|
|
.s_axi_arready(S_AXI_ARREADY_ram),
|
322 |
|
|
// R CHANNEL
|
323 |
|
|
.s_axi_rid(),
|
324 |
|
|
.s_axi_rdata(S_AXI_R_ram),
|
325 |
|
|
.s_axi_rresp(),
|
326 |
|
|
.s_axi_rlast(S_AXI_RLAST_ram),
|
327 |
|
|
.s_axi_rvalid(S_AXI_RVALID_ram),
|
328 |
|
|
.s_axi_rready(S_AXI_RREADY_ram),
|
329 |
|
|
|
330 |
|
|
.init_calib_complete(init_calib_complete),
|
331 |
|
|
.sys_rst(~locked)
|
332 |
|
|
);
|
333 |
|
|
|
334 |
|
|
axi_rom bootrom (
|
335 |
|
|
.clk(clk),
|
336 |
|
|
.rstn(rstn_ddr),
|
337 |
|
|
.axi_ARVALID(S_AXI_ARVALID_rom),
|
338 |
|
|
.axi_ARREADY(S_AXI_ARREADY_rom),
|
339 |
|
|
.axi_AR(S_AXI_AR_rom),
|
340 |
|
|
.axi_ARBURST(S_AXI_ARBURST_rom),
|
341 |
|
|
.axi_ARLEN(S_AXI_ARLEN_rom),
|
342 |
|
|
.axi_RLAST(S_AXI_RLAST_rom),
|
343 |
|
|
.axi_R(S_AXI_R_rom),
|
344 |
|
|
.axi_RVALID(S_AXI_RVALID_rom),
|
345 |
|
|
.axi_RREADY(S_AXI_RREADY_rom)
|
346 |
|
|
);
|
347 |
|
|
|
348 |
|
|
axi_ethernetlite_0 i_etherlite (
|
349 |
|
|
.s_axi_aclk(clk),
|
350 |
|
|
.s_axi_aresetn(rstn_ddr),
|
351 |
|
|
|
352 |
|
|
.ip2intc_irpt(int_net),
|
353 |
|
|
|
354 |
|
|
.s_axi_awid(4'b000),
|
355 |
|
|
.s_axi_awaddr(S_AXI_AW_net[12:0]),
|
356 |
|
|
.s_axi_awlen(S_AXI_AWLEN_net),
|
357 |
|
|
.s_axi_awsize(S_AXI_AWSIZE_net),
|
358 |
|
|
.s_axi_awburst(S_AXI_AWBURST_net),
|
359 |
|
|
.s_axi_awcache(4'b0000),
|
360 |
|
|
.s_axi_awvalid(S_AXI_AWVALID_net),
|
361 |
|
|
.s_axi_awready(S_AXI_AWREADY_net),
|
362 |
|
|
.s_axi_wdata(S_AXI_W_net),
|
363 |
|
|
.s_axi_wstrb(S_AXI_WSTRB_net),
|
364 |
|
|
.s_axi_wlast(S_AXI_WLAST_net),
|
365 |
|
|
.s_axi_wvalid(S_AXI_WVALID_net),
|
366 |
|
|
.s_axi_wready(S_AXI_WREADY_net),
|
367 |
|
|
.s_axi_bid(),
|
368 |
|
|
.s_axi_bresp(),
|
369 |
|
|
.s_axi_bvalid(),
|
370 |
|
|
.s_axi_bready(1'b1),
|
371 |
|
|
.s_axi_arid(4'b0),
|
372 |
|
|
.s_axi_araddr(S_AXI_AR_net[12:0]),
|
373 |
|
|
.s_axi_arlen(S_AXI_ARLEN_net),
|
374 |
|
|
.s_axi_arsize(S_AXI_ARSIZE_net),
|
375 |
|
|
.s_axi_arburst(S_AXI_ARBURST_net),
|
376 |
|
|
.s_axi_arcache(4'b0),
|
377 |
|
|
.s_axi_arvalid(S_AXI_ARVALID_net),
|
378 |
|
|
.s_axi_arready(S_AXI_ARREADY_net),
|
379 |
|
|
.s_axi_rid(),
|
380 |
|
|
.s_axi_rdata(S_AXI_R_net),
|
381 |
|
|
.s_axi_rresp(),
|
382 |
|
|
.s_axi_rlast(S_AXI_RLAST_net),
|
383 |
|
|
.s_axi_rvalid(S_AXI_RVALID_net),
|
384 |
|
|
.s_axi_rready(S_AXI_RREADY_net),
|
385 |
|
|
// to RMII converter
|
386 |
|
|
.phy_tx_clk(rmii2mac_tx_clk),
|
387 |
|
|
.phy_rx_clk(rmii2mac_rx_clk),
|
388 |
|
|
.phy_crs(rmii2mac_crs),
|
389 |
|
|
.phy_dv(rmii2mac_rx_dv),
|
390 |
|
|
.phy_rx_data(rmii2mac_rxd),
|
391 |
|
|
.phy_tx_data(mac2rmii_txd),
|
392 |
|
|
.phy_col(rmii2mac_col),
|
393 |
|
|
.phy_rx_er(rmii2mac_rx_er),
|
394 |
|
|
.phy_tx_en(mac2rmii_tx_en),
|
395 |
|
|
|
396 |
|
|
//.phy_tx_data(PhyTxd),
|
397 |
|
|
.phy_rst_n(PhyRstn),
|
398 |
|
|
.phy_mdio_i(PhyMdio_i),
|
399 |
|
|
.phy_mdio_o(PhyMdio_o),
|
400 |
|
|
.phy_mdio_t(PhyMdio_t),
|
401 |
|
|
.phy_mdc(PhyMdc)
|
402 |
|
|
);
|
403 |
|
|
|
404 |
|
|
IOBUF i_iobuf_mdio(
|
405 |
|
|
.O(PhyMdio_i),
|
406 |
|
|
.IO(PhyMdio),
|
407 |
|
|
.I(PhyMdio_o),
|
408 |
|
|
.T(PhyMdio_t));
|
409 |
|
|
|
410 |
|
|
axi_crossbar_0 i_axi_crossbar_0 (
|
411 |
|
|
.aclk(clk),
|
412 |
|
|
.aresetn(rstn_ddr),
|
413 |
|
|
|
414 |
|
|
.m_axi_awaddr({S_AXI_AW_net,S_AXI_AW_rom,S_AXI_AW_ram}),
|
415 |
|
|
.m_axi_awlen({S_AXI_AWLEN_net,S_AXI_AWLEN_rom,S_AXI_AWLEN_ram}),
|
416 |
|
|
.m_axi_awsize({S_AXI_AWSIZE_net,S_AXI_AWSIZE_rom,S_AXI_AWSIZE_ram}),
|
417 |
|
|
.m_axi_awburst({S_AXI_AWBURST_net,S_AXI_AWBURST_rom,S_AXI_AWBURST_ram}),
|
418 |
|
|
.m_axi_awlock(),
|
419 |
|
|
.m_axi_awcache(),
|
420 |
|
|
.m_axi_awprot(),
|
421 |
|
|
.m_axi_awqos(),
|
422 |
|
|
.m_axi_awuser(),
|
423 |
|
|
.m_axi_awvalid({S_AXI_AWVALID_net,S_AXI_AWVALID_rom,S_AXI_AWVALID_ram}),
|
424 |
|
|
.m_axi_awready({S_AXI_AWREADY_net,1'b1,S_AXI_AWREADY_ram}),
|
425 |
|
|
|
426 |
|
|
.m_axi_wdata({S_AXI_W_net,S_AXI_W_rom,S_AXI_W_ram}),
|
427 |
|
|
.m_axi_wstrb({S_AXI_WSTRB_net,S_AXI_WSTRB_rom,S_AXI_WSTRB_ram}),
|
428 |
|
|
.m_axi_wlast({S_AXI_WLAST_net,S_AXI_WLAST_rom,S_AXI_WLAST_ram}),
|
429 |
|
|
.m_axi_wuser(),
|
430 |
|
|
.m_axi_wvalid({S_AXI_WVALID_net,S_AXI_WVALID_rom,S_AXI_WVALID_ram}),
|
431 |
|
|
.m_axi_wready({S_AXI_WREADY_net,1'b1,S_AXI_WREADY_ram}),
|
432 |
|
|
|
433 |
|
|
.m_axi_bresp(0),
|
434 |
|
|
.m_axi_buser(0),
|
435 |
|
|
.m_axi_bvalid(3'b111),
|
436 |
|
|
.m_axi_bready(),
|
437 |
|
|
|
438 |
|
|
.m_axi_araddr({S_AXI_AR_net,S_AXI_AR_rom,S_AXI_AR_ram}),
|
439 |
|
|
.m_axi_arlen({S_AXI_ARLEN_net,S_AXI_ARLEN_rom,S_AXI_ARLEN_ram}),
|
440 |
|
|
.m_axi_arsize({S_AXI_ARSIZE_net,S_AXI_ARSIZE_rom,S_AXI_ARSIZE_ram}),
|
441 |
|
|
.m_axi_arburst({S_AXI_ARBURST_net,S_AXI_ARBURST_rom,S_AXI_ARBURST_ram}),
|
442 |
|
|
.m_axi_arlock(),
|
443 |
|
|
.m_axi_arcache(),
|
444 |
|
|
.m_axi_arprot(),
|
445 |
|
|
.m_axi_arqos(),
|
446 |
|
|
.m_axi_aruser(),
|
447 |
|
|
.m_axi_arvalid({S_AXI_ARVALID_net,S_AXI_ARVALID_rom,S_AXI_ARVALID_ram}),
|
448 |
|
|
.m_axi_arready({S_AXI_ARREADY_net,S_AXI_ARREADY_rom,S_AXI_ARREADY_ram}),
|
449 |
|
|
|
450 |
|
|
.m_axi_rdata({S_AXI_R_net,S_AXI_R_rom,S_AXI_R_ram}),
|
451 |
|
|
.m_axi_rresp(6'b0),
|
452 |
|
|
.m_axi_rlast({S_AXI_RLAST_net,S_AXI_RLAST_rom,S_AXI_RLAST_ram}),
|
453 |
|
|
.m_axi_ruser(12'b0),
|
454 |
|
|
.m_axi_rvalid({S_AXI_RVALID_net,S_AXI_RVALID_rom,S_AXI_RVALID_ram}),
|
455 |
|
|
.m_axi_rready({S_AXI_RREADY_net,S_AXI_RREADY_rom,S_AXI_RREADY_ram}),
|
456 |
|
|
|
457 |
|
|
.s_axi_awaddr(M_AXI_AW), .s_axi_awvalid(M_AXI_AWVALID), .s_axi_awready(M_AXI_AWREADY),
|
458 |
|
|
.s_axi_awburst(M_AXI_AWBURST), .s_axi_awlen(M_AXI_AWLEN), .s_axi_awsize(M_AXI_AWSIZE),
|
459 |
|
|
.s_axi_wdata(M_AXI_W), .s_axi_wvalid(M_AXI_WVALID), .s_axi_wready(M_AXI_WREADY), .s_axi_wstrb(M_AXI_WSTRB), .s_axi_wlast(M_AXI_WLAST),
|
460 |
|
|
.s_axi_araddr(M_AXI_AR), .s_axi_arvalid(M_AXI_ARVALID), .s_axi_arready(M_AXI_ARREADY),
|
461 |
|
|
.s_axi_arburst(M_AXI_ARBURST), .s_axi_arlen(M_AXI_ARLEN), .s_axi_arsize(M_AXI_ARSIZE),
|
462 |
|
|
.s_axi_rdata(M_AXI_R), .s_axi_rvalid(M_AXI_RVALID), .s_axi_rready(M_AXI_RREADY), .s_axi_rlast(M_AXI_RLAST),
|
463 |
|
|
.s_axi_bvalid(),.s_axi_bready(1'b1),
|
464 |
|
|
.s_axi_arlock(0), .s_axi_arcache(0),.s_axi_arprot(0), .s_axi_arqos(0), .s_axi_aruser(0),
|
465 |
|
|
.s_axi_awlock(0), .s_axi_awcache(0),.s_axi_awprot(0), .s_axi_awqos(0), .s_axi_awuser(0),
|
466 |
|
|
.s_axi_wuser(0)
|
467 |
|
|
);
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
always @(posedge clk) if (rstn_ddr == 0) sdreset <=1; else sdreset <=0;
|
471 |
|
|
always @(posedge clk) if (rstn_ddr == 0) PhyClk50Mhz <=0; else PhyClk50Mhz <=~PhyClk50Mhz;
|
472 |
|
|
|
473 |
|
|
assign gpioA[0] = (gpioA_dir[0] == 0) ? 1'bz : gpioA_out[0];
|
474 |
|
|
assign gpioA[1] = (gpioA_dir[1] == 0) ? 1'bz : gpioA_out[1];
|
475 |
|
|
assign gpioA[2] = (gpioA_dir[2] == 0) ? 1'bz : gpioA_out[2];
|
476 |
|
|
assign gpioA[3] = (gpioA_dir[3] == 0) ? 1'bz : gpioA_out[3];
|
477 |
|
|
assign gpioA[4] = (gpioA_dir[4] == 0) ? 1'bz : gpioA_out[4];
|
478 |
|
|
assign gpioA[5] = (gpioA_dir[5] == 0) ? 1'bz : gpioA_out[5];
|
479 |
|
|
assign gpioA[6] = (gpioA_dir[6] == 0) ? 1'bz : gpioA_out[6];
|
480 |
|
|
assign gpioA[7] = (gpioA_dir[7] == 0) ? 1'bz : gpioA_out[7];
|
481 |
|
|
assign gpioB[0] = (gpioB_dir[0] == 0) ? 1'bz : gpioB_out[0];
|
482 |
|
|
assign gpioB[1] = (gpioB_dir[1] == 0) ? 1'bz : gpioB_out[1];
|
483 |
|
|
assign gpioB[2] = (gpioB_dir[2] == 0) ? 1'bz : gpioB_out[2];
|
484 |
|
|
assign gpioB[3] = (gpioB_dir[3] == 0) ? 1'bz : gpioB_out[3];
|
485 |
|
|
assign gpioB[4] = (gpioB_dir[4] == 0) ? 1'bz : gpioB_out[4];
|
486 |
|
|
assign gpioB[5] = (gpioB_dir[5] == 0) ? 1'bz : gpioB_out[5];
|
487 |
|
|
assign gpioB[6] = (gpioB_dir[6] == 0) ? 1'bz : gpioB_out[6];
|
488 |
|
|
assign gpioB[7] = (gpioB_dir[7] == 0) ? 1'bz : gpioB_out[7];
|
489 |
|
|
assign sdwp = 1'b1;
|
490 |
|
|
assign sdhld = 1'b1;
|
491 |
|
|
|
492 |
|
|
periph i_periph (
|
493 |
|
|
.s00_AXI_RSTN(rstn_ddr),
|
494 |
|
|
.s00_AXI_CLK(clk),
|
495 |
|
|
.cfg(gpio_in[6:0]),
|
496 |
|
|
// spi
|
497 |
|
|
.spi_mosi(sdout),
|
498 |
|
|
.spi_miso(sdin),
|
499 |
|
|
.spi_clk(sdclk),
|
500 |
|
|
.spi_cs(sdcs),
|
501 |
|
|
// tiny spi
|
502 |
|
|
.mosi(mosi),
|
503 |
|
|
.miso(miso),
|
504 |
|
|
.sclk(sclk),
|
505 |
|
|
// interrupts
|
506 |
|
|
.int_pic(int_pic),
|
507 |
|
|
.iack(iack),
|
508 |
|
|
.ivect(ivect),
|
509 |
|
|
.int_bus({aclInt2,aclInt1,int_net,1'b0}),
|
510 |
|
|
// gpio
|
511 |
|
|
.gpioA_in(gpioA),.gpioB_in(gpioB),
|
512 |
|
|
.gpioA_out(gpioA_out),.gpioB_out(gpioB_out),
|
513 |
|
|
.gpioA_dir(gpioA_dir),.gpioB_dir(gpioB_dir),
|
514 |
|
|
//uart
|
515 |
|
|
.RXD(RXD),
|
516 |
|
|
.TXD(TXD),
|
517 |
|
|
// AXI4 IO 32 BIT BUS
|
518 |
|
|
.s00_AXI_AWADDR(M_IO_AXI_AW),
|
519 |
|
|
.s00_AXI_AWVALID(M_IO_AXI_AWVALID),
|
520 |
|
|
.s00_AXI_AWREADY(M_IO_AXI_AWREADY),
|
521 |
|
|
.s00_AXI_AWBURST(M_IO_AXI_AWBURST),
|
522 |
|
|
.s00_AXI_AWLEN(M_IO_AXI_AWLEN),
|
523 |
|
|
.s00_AXI_AWSIZE(M_IO_AXI_AWSIZE),
|
524 |
|
|
.s00_AXI_ARADDR(M_IO_AXI_AR),
|
525 |
|
|
.s00_AXI_ARVALID(M_IO_AXI_ARVALID),
|
526 |
|
|
.s00_AXI_ARREADY(M_IO_AXI_ARREADY),
|
527 |
|
|
.s00_AXI_ARBURST(M_IO_AXI_ARBURST),
|
528 |
|
|
.s00_AXI_ARLEN(M_IO_AXI_ARLEN),
|
529 |
|
|
.s00_AXI_ARSIZE(M_IO_AXI_ARSIZE),
|
530 |
|
|
.s00_AXI_WDATA(M_IO_AXI_W),
|
531 |
|
|
.s00_AXI_WVALID(M_IO_AXI_WVALID),
|
532 |
|
|
.s00_AXI_WREADY(M_IO_AXI_WREADY),
|
533 |
|
|
.s00_AXI_WSTRB(M_IO_AXI_WSTRB),
|
534 |
|
|
.s00_AXI_WLAST(M_IO_AXI_WLAST),
|
535 |
|
|
.s00_AXI_RDATA(M_IO_AXI_R),
|
536 |
|
|
.s00_AXI_RVALID(M_IO_AXI_RVALID),
|
537 |
|
|
.s00_AXI_RREADY(M_IO_AXI_RREADY),
|
538 |
|
|
.s00_AXI_RLAST(M_IO_AXI_RLAST),
|
539 |
|
|
.s00_AXI_BVALID(),
|
540 |
|
|
.s00_AXI_BREADY(1'b1)
|
541 |
|
|
);
|
542 |
|
|
|
543 |
|
|
`ifndef simu
|
544 |
|
|
mii_to_rmii_0 mii_to_rmii_i (
|
545 |
|
|
.rst_n(PhyRstn),
|
546 |
|
|
.ref_clk(PhyClk50Mhz),
|
547 |
|
|
// to/from mac
|
548 |
|
|
.mac2rmii_tx_en(mac2rmii_tx_en),
|
549 |
|
|
.mac2rmii_txd(mac2rmii_txd),
|
550 |
|
|
.mac2rmii_tx_er(mac2rmii_tx_er),
|
551 |
|
|
.rmii2mac_tx_clk(rmii2mac_tx_clk),
|
552 |
|
|
.rmii2mac_rx_clk(rmii2mac_rx_clk),
|
553 |
|
|
.rmii2mac_col(rmii2mac_col),
|
554 |
|
|
.rmii2mac_crs(rmii2mac_crs),
|
555 |
|
|
.rmii2mac_rx_dv(rmii2mac_rx_dv),
|
556 |
|
|
.rmii2mac_rx_er(rmii2mac_rx_er),
|
557 |
|
|
.rmii2mac_rxd(rmii2mac_rxd),
|
558 |
|
|
// external connections
|
559 |
|
|
.phy2rmii_crs_dv(PhyCrs),
|
560 |
|
|
.phy2rmii_rx_er(PhyRxErr),
|
561 |
|
|
.phy2rmii_rxd(PhyRxd),
|
562 |
|
|
.rmii2phy_txd(PhyTxd),
|
563 |
|
|
.rmii2phy_tx_en(PhyTxEn)
|
564 |
|
|
);
|
565 |
|
|
`endif
|
566 |
|
|
|
567 |
|
|
endmodule
|