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[/] [v6502/] [trunk/] [alu_bin.vhd] - Blame information for rev 4

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1 4 Valerio63 
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8 bit binary alu
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-- Written by Valerio Venturi
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entity alu_bin is
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  port( alu_byp:  in STD_LOGIC;                      -- ALU bypass (no operation)
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            cin:  in STD_LOGIC;                      -- carry/borrow in
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            vin:  in STD_LOGIC;                      -- overflow in
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            op1:  in STD_LOGIC_VECTOR(7 downto 0);   -- 8 bit operand #1
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            op2:  in STD_LOGIC_VECTOR(7 downto 0);   -- 8 bit operand #2
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             fc:  in STD_LOGIC_VECTOR(5 downto 0);   -- function code (bit #0 serves as flag to signal an branch negative offset)
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             cf: out STD_LOGIC;                      -- carry/borrow out
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             zf: out STD_LOGIC;                      -- zero flag out
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             nf: out STD_LOGIC;                      -- negative flag out
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             vf: out STD_LOGIC;                      -- overflow flag out
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          pc_cf: out STD_LOGIC;                      -- carry/borrow out for PC operation
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         bcd_ol: out STD_LOGIC;                      -- bcd lsb overflow
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         bcd_oh: out STD_LOGIC;                      -- bcd msb overflow
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           dout: out STD_LOGIC_VECTOR(7 downto 0)    -- 8 bit result out
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      );
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end alu_bin;
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architecture comb of alu_bin is
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-- ALU function codes
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constant NOP_A: STD_LOGIC_VECTOR(5 downto 0) := "000000";    -- no operation
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constant SUM_A: STD_LOGIC_VECTOR(5 downto 0) := "000010";    -- sum with carry
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constant SUB_A: STD_LOGIC_VECTOR(5 downto 0) := "000100";    -- subtract with borrow
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constant AND_A: STD_LOGIC_VECTOR(5 downto 0) := "000110";    -- and
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constant  OR_A: STD_LOGIC_VECTOR(5 downto 0) := "001000";    -- or
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constant XOR_A: STD_LOGIC_VECTOR(5 downto 0) := "001010";    -- xor
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constant INC_A: STD_LOGIC_VECTOR(5 downto 0) := "001100";    -- increment by 1
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constant DEC_A: STD_LOGIC_VECTOR(5 downto 0) := "001110";    -- decrement by 1
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constant SHL_A: STD_LOGIC_VECTOR(5 downto 0) := "010000";    -- shift left
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constant SHR_A: STD_LOGIC_VECTOR(5 downto 0) := "010010";    -- shift right
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constant ROL_A: STD_LOGIC_VECTOR(5 downto 0) := "010100";    -- rotation left
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constant ROR_A: STD_LOGIC_VECTOR(5 downto 0) := "010110";    -- rotation right
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constant SWC_A: STD_LOGIC_VECTOR(5 downto 0) := "011000";    -- sum without carry (used for indexing and branches)
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constant SWC_N: STD_LOGIC_VECTOR(5 downto 0) := "011001";    -- subtract without borrow (used only by branches with negative offset)
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constant BIT_A: STD_LOGIC_VECTOR(5 downto 0) := "011010";    -- bit test (used by BIT opcode)
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constant DAA_A: STD_LOGIC_VECTOR(5 downto 0) := "011100";    -- decimal adjustement for BCD sum
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constant DAS_A: STD_LOGIC_VECTOR(5 downto 0) := "011110";    -- decimal adjustement for BCD subtract
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constant CMP_A: STD_LOGIC_VECTOR(5 downto 0) := "100000";    -- compare
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constant TSB_A: STD_LOGIC_VECTOR(5 downto 0) := "100010";    -- test and set bit
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constant TRB_A: STD_LOGIC_VECTOR(5 downto 0) := "100100";    -- test and reset bit
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signal      op: STD_LOGIC_VECTOR(5 downto 0);
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signal       c: STD_LOGIC;
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signal    pc_c: STD_LOGIC;
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signal   v_add: STD_LOGIC;
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signal   v_sub: STD_LOGIC;
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signal   bcd_l: STD_LOGIC;
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signal   bcd_h: STD_LOGIC;
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signal  bcd_lh: STD_LOGIC;
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signal   n_op2: STD_LOGIC_VECTOR(7 downto 0);
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signal       y: STD_LOGIC_VECTOR(8 downto 0);
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begin
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  process(fc)
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  begin
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    case fc is
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      when SWC_A  => op             <= SWC_A;
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      when SWC_N  => op             <= SWC_N;
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      when others => op(5 downto 1) <= fc(5 downto 1);
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                     op(0)          <= '0';
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    end case;
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  end process;
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  n_op2 <= (not op2);
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  process(alu_byp,op,op1,op2,n_op2,cin)
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  begin
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    if alu_byp = '1' then
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      y(y'left) <= '0';
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      y(y'left-1 downto y'right) <= op1;
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    else
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      case op is
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        when SUM_A  => y <= ('0' & op1) + ('0' & op2) + ("00000000" & cin);     -- ADC with carry in
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        when SUB_A  => y <= ('0' & op1) + ('0' & n_op2) + ("00000000" & cin);   -- SBC with borrow in
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        when BIT_A  => y <= ('0' & op1) and ('0' & op2);                        -- BIT test
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        when AND_A  => y <= ('0' & op1) and ('0' & op2);                        -- AND
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        when OR_A   => y <= ('0' & op1)  or ('0' & op2);                        -- OR
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        when XOR_A  => y <= ('0' & op1) xor ('0' & op2);                        -- XOR
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        when INC_A  => y <= op1 + "000000001";                                  -- INC
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        when DEC_A  => y <= op1 - "000000001";                                  -- DEC
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        when SHL_A  => y(8 downto 1) <= op1; y(0) <= '0';                       -- ASL
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        when SHR_A  => y <= "00" & op1(op1'left downto op1'right+1);            -- LSR
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        when ROL_A  => y(8 downto 1) <= op1; y(0) <= cin;                       -- ROL
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        when ROR_A  => y <= '0' & cin & op1(op1'left downto op1'right+1);       -- ROR
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        when SWC_A  => y <= ('0' & op1) + ('0' & op2);                          -- ADD without carry in
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        when SWC_N  => y <= ('0' & op1) - ('0' & (0 - op2));                    -- SUB two complement without borrow in
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        when DAA_A  => y <= ('0' & op1) + ('0' & op2);                          -- ADD without carry in (used for DAA decimal adjustement)
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        when DAS_A  => y <= ('0' & op1) - ('0' & op2);                          -- SUB without borrow in (used for DAS decimal adjustement)
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        when CMP_A  => y <= ('1' & op1) - ('0' & op2);                          -- SBC without borrow in (used for compare)
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        when TSB_A  => y <= ('0' & op1) or ('0' & op2);                         -- TSB
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        when TRB_A  => y <= ('0' & not op1) and ('0' & op2);                    -- TRB
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        when others => y(y'left) <= '0'; y(y'left-1 downto y'right) <= op1;     -- NOP
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      end case;
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    end if;
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  end process;
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  -- flag "C" carry/borrow logic
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  process(op,op1,y,cin)
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  begin
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    case op is
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      when SUM_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when SUB_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when SWC_A  => pc_c <= y(y'left);
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                     c    <= cin;
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      when SWC_N  => pc_c <= not y(y'left);
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                     c    <= cin;
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      when SHL_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when SHR_A  => c    <= op1(op1'right);
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                     pc_c <= '0';
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      when ROL_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when ROR_A  => c    <= op1(op1'right);
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                     pc_c <= '0';
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      when DAA_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when DAS_A  => c    <= cin;
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                     pc_c <= '0';
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      when BIT_A  => c    <= cin;
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                     pc_c <= '0';
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      when CMP_A  => c    <= y(y'left);
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                     pc_c <= '0';
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      when others => c    <= cin;
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                     pc_c <= '0';
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    end case;
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  end process;
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  -- flag "V" overflow logic
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  v_add <= (y(7) xor op1(7)) and not (op1(7) xor op2(7));
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  v_sub <= (y(7) xor op1(7)) and (op1(7) xor op2(7));
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  process(op,op2,v_add,v_sub,vin)
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  begin
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    case op is
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      when SUM_A  => vf <= v_add;
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      when SUB_A  => vf <= v_sub;
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      when BIT_A  => vf <= op2(op2'left-1);
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      when others => vf <= vin;
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    end case;
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  end process;
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  -- flag "N" negative result logic
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  process(op,op2,y)
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  begin
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    case op is
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      when BIT_A  => nf <= op2(op2'left);
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      when others => nf <= y(y'left-1);
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    end case;
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  end process;
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  -- flag "Z" zero result logic (always set with zero results)
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  zf <= '1' when y(y'left-1 downto y'right) = "00000000" else '0';
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  -- bcd adjustement detection
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  process(y)
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  begin
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    case y(3 downto 0) is
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      when "1010" => bcd_l <= '1';  -- 0xA
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      when "1011" => bcd_l <= '1';  -- 0xB
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      when "1100" => bcd_l <= '1';  -- 0xC
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      when "1101" => bcd_l <= '1';  -- 0xD
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      when "1110" => bcd_l <= '1';  -- 0xE
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      when "1111" => bcd_l <= '1';  -- 0xF
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      when others => bcd_l <= '0';
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    end case;
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    case y(7 downto 4) is
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      when "1010" => bcd_h <= '1';  -- 0xA
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      when "1011" => bcd_h <= '1';  -- 0xB
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      when "1100" => bcd_h <= '1';  -- 0xC
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      when "1101" => bcd_h <= '1';  -- 0xD
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      when "1110" => bcd_h <= '1';  -- 0xE
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      when "1111" => bcd_h <= '1';  -- 0xF
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      when others => bcd_h <= '0';
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    end case;
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  end process;
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  process(y)
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  begin
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    case y(7 downto 0) is
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      when "10011010" => bcd_lh <= '1';  -- 0x9A
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      when "10011011" => bcd_lh <= '1';  -- 0x9B
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      when "10011100" => bcd_lh <= '1';  -- 0x9C
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      when "10011101" => bcd_lh <= '1';  -- 0x9D
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      when "10011110" => bcd_lh <= '1';  -- 0x9E
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      when "10011111" => bcd_lh <= '1';  -- 0x9F
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      when others     => bcd_lh <= '0';
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    end case;
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  end process;
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  bcd_ol <= bcd_l or bcd_lh;
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  bcd_oh <= bcd_h or bcd_lh;
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  cf <= c;
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  pc_cf <= pc_c;
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  dout <= y(y'left-1 downto y'right);
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end comb;
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