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[/] [v6502/] [trunk/] [mcpla.vhd] - Blame information for rev 4

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1 4 Valerio63 
library IEEE;
2 
use IEEE.std_logic_1164.all;  -- defines std_logic types
3 
use IEEE.STD_LOGIC_unsigned.all;
4 
use IEEE.STD_LOGIC_arith.all;
5 
 
6 
-- microcode PLA (NMOS 6502 opcode mask covering)
7 
-- Written by Valerio Venturi
8 
-- output fields format:
9 
-- fields:
10 
-- RSEL:  registers output multiplexer select
11 
-- REGOP: registers load/increment/decrement etc.
12 
-- ALUOP: ALU operation
13 
-- P_OP:  register P set/reset bit
14 
-- MPR:   register MP
15 
-- PCR:   register PC
16 
-- CLI:   clear interrupt request
17 
-- BR:    branch opcode
18 
-- EI:    end of microcode sequence
19 
-- W:     read/write control
20 
-- PD:    PC/MP output multiplexer select
21 
entity mcpla is
22 
  port(    a:  in STD_LOGIC_VECTOR(10 downto 0);
23 
           q: out STD_LOGIC_VECTOR(34 downto 0)
24 
      );
25 
end mcpla;
26 
 
27 
architecture comb of mcpla is
28 
 
29 
------------------------------------
30 
--            IMPLIED             --
31 
------------------------------------
32 
constant   NOP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101010000"; -- 0xEA NOP
33 
 
34 
-- interrupts
35 
constant   BRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000000000"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000000001"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000000010"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000000011"; -- 0x00 BRK/IRQ/NMI/RES
39 
constant   BRK_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000000100"; -- 0x00 BRK/IRQ/NMI/RES
40 
constant   BRK_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00000000101"; -- 0x00 BRK/IRQ/NMI/RES
41 
constant   BRK_OP6: STD_LOGIC_VECTOR(10 downto 0) := "00000000110"; -- 0x00 BRK/IRQ/NMI/RES
42 
 
43 
-- IMPLIED
44 
constant   CLC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011000000"; -- 0x18 CLC 0->C
45 
constant   SEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111000000"; -- 0x38 SEC 1->C
46 
constant   CLI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011000000"; -- 0x58 CLI 0->I
47 
constant   SEI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111000000"; -- 0x78 SEI 1->I
48 
constant   CLV_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111000000"; -- 0xB8 CLV 0->V
49 
constant   CLD_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011000000"; -- 0xD8 CLD 0->D
50 
constant   SED_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111000000"; -- 0xF8 SED 1->D
51 
constant   TAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101010000"; -- 0xAA TAX A->X
52 
constant   TAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101000000"; -- 0xA8 TAY A->Y
53 
constant   TXA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001010000"; -- 0x8A TXA X->A
54 
constant   TYA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011000000"; -- 0x98 TYA Y->A
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constant   TXY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011011000"; -- 0x9B TXY X->Y
56 
constant   TYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111011000"; -- 0xBB TYX Y->X
57 
constant   TXS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011010000"; -- 0x9A TXS X->S
58 
constant   TSX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111010000"; -- 0xBA TSX S->X
59 
constant   TAZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011011000"; -- 0x1B TAZ A->Z
60 
constant   TZA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111011000"; -- 0x3B TZA Z->A
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constant   PHP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001000000"; -- 0x08 PHP P->S
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constant   PHA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001000000"; -- 0x48 PHA A->S
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constant   PHX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011010000"; -- 0xDA PHX X->S
64 
constant   PHY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011010000"; -- 0x5A PHY X->S
65 
constant   PHR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001011000"; -- 0x8B PHR AXY->S
66 
constant   PHR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001011001"; -- 0x8B PHR AXY->S
67 
constant   PHR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001011010"; -- 0x8B PHR AXY->S
68 
constant   PLP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101000000"; -- 0x28 PLP S->P
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constant   PLP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101000001"; -- 0x28 PLP S->P
70 
constant   PLA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101000000"; -- 0x68 PLA S->A
71 
constant   PLA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101000001"; -- 0x68 PLA S->A
72 
constant   PLX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111010000"; -- 0xFA PLX S->X
73 
constant   PLX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111010001"; -- 0xFA PLX S->X
74 
constant   PLY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111010000"; -- 0x7A PLY S->Y
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constant   PLY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111010001"; -- 0x7A PLY S->Y
76 
constant   PLR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101011000"; -- 0xAB PLR S->YXA
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constant   PLR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101011001"; -- 0xAB PLR S->YXA
78 
constant   PLR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101011010"; -- 0xAB PLR S->YXA
79 
constant   PLR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10101011011"; -- 0xAB PLR S->YXA
80 
constant   INC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011010000"; -- 0x1A INC A +1
81 
constant   DEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111010000"; -- 0x3A DEC A -1
82 
constant   INX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101000000"; -- 0xE8 INX X +1
83 
constant   DEX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001010000"; -- 0xCA DEX X -1
84 
constant   INY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001000000"; -- 0xC8 INY Y +1
85 
constant   DEY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001000000"; -- 0x88 DEY Y -1
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constant   RTS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100000000"; -- 0x60 RTS
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constant   RTS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100000001"; -- 0x60 RTS
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constant   RTS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100000010"; -- 0x60 RTS
89 
constant   RTS_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100000011"; -- 0x60 RTS
90 
constant   RTS_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100000100"; -- 0x60 RTS
91 
constant   RTI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000000000"; -- 0x40 RTI
92 
constant   RTI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000000001"; -- 0x40 RTI
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constant   RTI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000000010"; -- 0x40 RTI
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constant   RTI_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000000011"; -- 0x40 RTI
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constant   RTI_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01000000100"; -- 0x40 RTI
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constant   RTI_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01000000101"; -- 0x40 RTI
97 
constant   ASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001010000"; -- 0x0A ASL A
98 
constant   LSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001010000"; -- 0x4A LSR A
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constant   ROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101010000"; -- 0x2A ROL A
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constant   ROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101010000"; -- 0x6A ROR A
101 
constant   XYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101011000"; -- 0xEB EXCHANGE X <-> Y
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constant   XYX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101011001"; -- 0xEB EXCHANGE X <-> Y
103 
constant   XYX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101011010"; -- 0xEB EXCHANGE X <-> Y
104 
constant   XAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001011000"; -- 0x0B EXCHANGE A <-> X
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constant   XAX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001011001"; -- 0x0B EXCHANGE A <-> X
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constant   XAX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001011010"; -- 0x0B EXCHANGE A <-> X
107 
constant   XAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101011000"; -- 0x2B EXCHANGE A <-> Y
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constant   XAY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101011001"; -- 0x2B EXCHANGE A <-> Y
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constant   XAY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101011010"; -- 0x2B EXCHANGE A <-> Y
110 
constant   ISP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001011000"; -- 0x4B init SP X -> S lsb; A -> S msb
111 
constant   ISP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001011001"; -- 0x4B init SP X -> S lsb; A -> S msb
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constant   TSP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011011000"; -- 0x5B transfer SP S lsb -> X; S msb -> A
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constant   TSP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011011001"; -- 0x5B transfer SP S lsb -> X; S msb -> A
114 
 
115 
------------------------------------
116 
--           IMMEDIATE            --
117 
------------------------------------
118 
constant IMLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101001000"; -- 0xA9 LDA #IMM
119 
constant IMLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100010000"; -- 0xA2 LDX #IMM
120 
constant IMLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100000000"; -- 0xA0 LDY #IMM
121 
constant IMADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101001000"; -- 0x69 ADC #IMM
122 
constant IMADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101001001"; -- 0x69 ADC #IMM
123 
constant IMSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101001000"; -- 0xE9 SBC #IMM
124 
constant IMSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101001001"; -- 0xE9 SBC #IMM
125 
constant IMAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101001000"; -- 0x29 AND #IMM
126 
constant IMORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001001000"; -- 0x09 ORA #IMM
127 
constant IMEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001001000"; -- 0x49 EOR #IMM
128 
constant IMCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001001000"; -- 0xC9 CMP #IMM
129 
constant IMCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100000000"; -- 0xE0 CPX #IMM
130 
constant IMCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000000000"; -- 0xC0 CPY #IMM
131 
constant IMBRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001001000"; -- 0x89 BRK #IMM
132 
 
133 
------------------------------------
134 
--           ZERO PAGE            --
135 
------------------------------------
136 
constant ZPLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100101000"; -- 0xA5 LDA ZP
137 
constant ZPLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100101001"; -- 0xA5 LDA ZP
138 
constant ZPLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100110000"; -- 0xA6 LDX ZP
139 
constant ZPLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100110001"; -- 0xA6 LDX ZP
140 
constant ZPLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100100000"; -- 0xA4 LDY ZP
141 
constant ZPLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100100001"; -- 0xA4 LDY ZP
142 
constant ZPSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000101000"; -- 0x85 STA ZP
143 
constant ZPSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000101001"; -- 0x85 STA ZP
144 
constant ZPSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000110000"; -- 0x86 STX ZP
145 
constant ZPSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000110001"; -- 0x86 STX ZP
146 
constant ZPSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000100000"; -- 0x84 STY ZP
147 
constant ZPSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000100001"; -- 0x84 STY ZP
148 
constant ZPSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100100000"; -- 0x64 STZ ZP
149 
constant ZPSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100100001"; -- 0x64 STZ ZP
150 
constant ZPADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100101000"; -- 0x65 ADC ZP
151 
constant ZPADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100101001"; -- 0x65 ADC ZP
152 
constant ZPADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100101010"; -- 0x65 ADC ZP
153 
constant ZPSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100101000"; -- 0xE5 SBC ZP
154 
constant ZPSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100101001"; -- 0xE5 SBC ZP
155 
constant ZPSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100101010"; -- 0xE5 SBC ZP
156 
constant ZPCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000101000"; -- 0xC5 CMP ZP
157 
constant ZPCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000101001"; -- 0xC5 CMP ZP
158 
constant ZPCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100100000"; -- 0xE4 CPX ZP
159 
constant ZPCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100100001"; -- 0xE4 CPX ZP
160 
constant ZPCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000100000"; -- 0xC4 CPY ZP
161 
constant ZPCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000100001"; -- 0xC4 CPY ZP
162 
constant ZPAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100101000"; -- 0x25 AND ZP
163 
constant ZPAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100101001"; -- 0x25 AND ZP
164 
constant ZPORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000101000"; -- 0x05 ORA ZP
165 
constant ZPORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000101001"; -- 0x05 ORA ZP
166 
constant ZPEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000101000"; -- 0x45 EOR ZP
167 
constant ZPEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000101001"; -- 0x45 EOR ZP
168 
constant ZPBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100100000"; -- 0x24 BIT ZP
169 
constant ZPBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100100001"; -- 0x24 BIT ZP
170 
constant ZPASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000110000"; -- 0x06 ASL ZP
171 
constant ZPASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000110001"; -- 0x06 ASL ZP
172 
constant ZPASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000110010"; -- 0x06 ASL ZP
173 
constant ZPASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000110011"; -- 0x06 ASL ZP
174 
constant ZPLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000110000"; -- 0x46 LSR ZP
175 
constant ZPLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000110001"; -- 0x46 LSR ZP
176 
constant ZPLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000110010"; -- 0x46 LSR ZP
177 
constant ZPLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000110011"; -- 0x46 LSR ZP
178 
constant ZPROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100110000"; -- 0x26 ROL ZP
179 
constant ZPROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100110001"; -- 0x26 ROL ZP
180 
constant ZPROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100110010"; -- 0x26 ROL ZP
181 
constant ZPROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100110011"; -- 0x26 ROL ZP
182 
constant ZPROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100110000"; -- 0x66 ROR ZP
183 
constant ZPROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100110001"; -- 0x66 ROR ZP
184 
constant ZPROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100110010"; -- 0x66 ROR ZP
185 
constant ZPROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100110011"; -- 0x66 ROR ZP
186 
constant ZPINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100110000"; -- 0xE6 INC ZP
187 
constant ZPINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100110001"; -- 0xE6 INC ZP
188 
constant ZPINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100110010"; -- 0xE6 INC ZP
189 
constant ZPINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100110011"; -- 0xE6 INC ZP
190 
constant ZPDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000110000"; -- 0xC6 DEC ZP
191 
constant ZPDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000110001"; -- 0xC6 DEC ZP
192 
constant ZPDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000110010"; -- 0xC6 DEC ZP
193 
constant ZPDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000110011"; -- 0xC6 DEC ZP
194 
constant ZPTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000100000"; -- 0x04 TSB ZP
195 
constant ZPTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000100001"; -- 0x04 TSB ZP
196 
constant ZPTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000100010"; -- 0x04 TSB ZP
197 
constant ZPTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000100011"; -- 0x04 TSB ZP
198 
constant ZPTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000100100"; -- 0x04 TSB ZP
199 
constant ZPTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010100000"; -- 0x14 TRB ZP
200 
constant ZPTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010100001"; -- 0x14 TRB ZP
201 
constant ZPTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010100010"; -- 0x14 TRB ZP
202 
constant ZPTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010100011"; -- 0x14 TRB ZP
203 
constant ZPTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010100100"; -- 0x14 TRB ZP
204 
 
205 
------------------------------------
206 
--          ZERO PAGE,X           --
207 
------------------------------------
208 
constant ZXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110101000"; -- 0xB5 LDA ZP,X
209 
constant ZXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110101001"; -- 0xB5 LDA ZP,X
210 
constant ZXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110101010"; -- 0xB5 LDA ZP,X
211 
constant ZXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110100000"; -- 0xB4 LDY ZP,X
212 
constant ZXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110100001"; -- 0xB4 LDY ZP,X
213 
constant ZXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110100010"; -- 0xB4 LDY ZP,X
214 
constant ZXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010101000"; -- 0x95 STA ZP,X
215 
constant ZXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010101001"; -- 0x95 STA ZP,X
216 
constant ZXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010101010"; -- 0x95 STA ZP,X
217 
constant ZXSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010100000"; -- 0x94 STY ZP,X
218 
constant ZXSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010100001"; -- 0x94 STY ZP,X
219 
constant ZXSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010100010"; -- 0x94 STY ZP,X
220 
constant ZXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110100000"; -- 0x74 STZ ZP,X
221 
constant ZXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110100001"; -- 0x74 STZ ZP,X
222 
constant ZXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110100010"; -- 0x74 STZ ZP,X
223 
constant ZXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110101000"; -- 0x75 ADC ZP,X
224 
constant ZXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110101001"; -- 0x75 ADC ZP,X
225 
constant ZXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110101010"; -- 0x75 ADC ZP,X
226 
constant ZXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110101011"; -- 0x75 ADC ZP,X
227 
constant ZXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110101000"; -- 0xF5 SBC ZP,X
228 
constant ZXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110101001"; -- 0xF5 SBC ZP,X
229 
constant ZXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110101010"; -- 0xF5 SBC ZP,X
230 
constant ZXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110101011"; -- 0xF5 SBC ZP,X
231 
constant ZXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010101000"; -- 0xD5 CMP ZP,X
232 
constant ZXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010101001"; -- 0xD5 CMP ZP,X
233 
constant ZXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010101010"; -- 0xD5 CMP ZP,X
234 
constant ZXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110101000"; -- 0x35 AND ZP,X
235 
constant ZXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110101001"; -- 0x35 AND ZP,X
236 
constant ZXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110101010"; -- 0x35 AND ZP,X
237 
constant ZXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010101000"; -- 0x15 ORA ZP,X
238 
constant ZXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010101001"; -- 0x15 ORA ZP,X
239 
constant ZXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010101010"; -- 0x15 ORA ZP,X
240 
constant ZXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010101000"; -- 0x55 EOR ZP,X
241 
constant ZXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010101001"; -- 0x55 EOR ZP,X
242 
constant ZXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010101010"; -- 0x55 EOR ZP,X
243 
constant ZXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010110000"; -- 0x16 ASL ZP,X
244 
constant ZXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010110001"; -- 0x16 ASL ZP,X
245 
constant ZXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010110010"; -- 0x16 ASL ZP,X
246 
constant ZXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010110011"; -- 0x16 ASL ZP,X
247 
constant ZXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010110100"; -- 0x16 ASL ZP,X
248 
constant ZXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010110000"; -- 0x56 LSR ZP,X
249 
constant ZXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010110001"; -- 0x56 LSR ZP,X
250 
constant ZXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010110010"; -- 0x56 LSR ZP,X
251 
constant ZXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010110011"; -- 0x56 LSR ZP,X
252 
constant ZXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010110100"; -- 0x56 LSR ZP,X
253 
constant ZXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110110000"; -- 0x36 ROL ZP,X
254 
constant ZXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110110001"; -- 0x36 ROL ZP,X
255 
constant ZXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110110010"; -- 0x36 ROL ZP,X
256 
constant ZXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110110011"; -- 0x36 ROL ZP,X
257 
constant ZXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110110100"; -- 0x36 ROL ZP,X
258 
constant ZXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110110000"; -- 0x76 ROR ZP,X
259 
constant ZXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110110001"; -- 0x76 ROR ZP,X
260 
constant ZXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110110010"; -- 0x76 ROR ZP,X
261 
constant ZXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110110011"; -- 0x76 ROR ZP,X
262 
constant ZXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110110100"; -- 0x76 ROR ZP,X
263 
constant ZXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010110000"; -- 0xD6 DEC ZP,X
264 
constant ZXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010110001"; -- 0xD6 DEC ZP,X
265 
constant ZXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010110010"; -- 0xD6 DEC ZP,X
266 
constant ZXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010110011"; -- 0xD6 DEC ZP,X
267 
constant ZXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010110100"; -- 0xD6 DEC ZP,X
268 
constant ZXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110110000"; -- 0xF6 INC ZP,X
269 
constant ZXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110110001"; -- 0xF6 INC ZP,X
270 
constant ZXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110110010"; -- 0xF6 INC ZP,X
271 
constant ZXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110110011"; -- 0xF6 INC ZP,X
272 
constant ZXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110110100"; -- 0xF6 INC ZP,X
273 
constant ZXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110100000"; -- 0x34 BIT ZP,X
274 
constant ZXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110100001"; -- 0x34 BIT ZP,X
275 
constant ZXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110100010"; -- 0x34 BIT ZP,X
276 
 
277 
------------------------------------
278 
--          ZERO PAGE,Y           --
279 
------------------------------------
280 
constant ZYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110110000"; -- 0xB6 LDX ZP,Y
281 
constant ZYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110110001"; -- 0xB6 LDX ZP,Y
282 
constant ZYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110110010"; -- 0xB6 LDX ZP,Y
283 
constant ZYSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010110000"; -- 0x96 STX ZP,Y
284 
constant ZYSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010110001"; -- 0x96 STX ZP,Y
285 
constant ZYSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010110010"; -- 0x96 STX ZP,Y
286 
 
287 
------------------------------------
288 
--           INDIRECT             --
289 
------------------------------------
290 
constant INJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101100000"; -- 0x6C JMP (IND)
291 
constant INJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101100001"; -- 0x6C JMP (IND)
292 
constant INJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101100010"; -- 0x6C JMP (IND)
293 
constant INJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101100011"; -- 0x6C JMP (IND)
294 
 
295 
------------------------------------
296 
--          INDIRECT,Y            --
297 
------------------------------------
298 
constant IYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110001000"; -- 0xB1 LDA (IND_ZP),Y
299 
constant IYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110001001"; -- 0xB1 LDA (IND_ZP),Y
300 
constant IYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110001010"; -- 0xB1 LDA (IND_ZP),Y
301 
constant IYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10110001011"; -- 0xB1 LDA (IND_ZP),Y
302 
constant IYLDA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10110001100"; -- 0xB1 LDA (IND_ZP),Y
303 
constant IYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010001000"; -- 0x91 STA (IND_ZP),Y
304 
constant IYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010001001"; -- 0x91 STA (IND_ZP),Y
305 
constant IYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010001010"; -- 0x91 STA (IND_ZP),Y
306 
constant IYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10010001011"; -- 0x91 STA (IND_ZP),Y
307 
constant IYSTA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10010001100"; -- 0x91 STA (IND_ZP),Y
308 
constant IYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110001000"; -- 0x71 ADC (IND_ZP),Y
309 
constant IYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110001001"; -- 0x71 ADC (IND_ZP),Y
310 
constant IYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110001010"; -- 0x71 ADC (IND_ZP),Y
311 
constant IYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110001011"; -- 0x71 ADC (IND_ZP),Y
312 
constant IYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110001100"; -- 0x71 ADC (IND_ZP),Y
313 
constant IYADC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01110001101"; -- 0x71 ADC (IND_ZP),Y
314 
constant IYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110001000"; -- 0xF1 SBC (IND_ZP),Y
315 
constant IYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110001001"; -- 0xF1 SBC (IND_ZP),Y
316 
constant IYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110001010"; -- 0xF1 SBC (IND_ZP),Y
317 
constant IYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110001011"; -- 0xF1 SBC (IND_ZP),Y
318 
constant IYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110001100"; -- 0xF1 SBC (IND_ZP),Y
319 
constant IYSBC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11110001101"; -- 0xF1 SBC (IND_ZP),Y
320 
constant IYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010001000"; -- 0xD1 CMP (IND_ZP),Y
321 
constant IYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010001001"; -- 0xD1 CMP (IND_ZP),Y
322 
constant IYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010001010"; -- 0xD1 CMP (IND_ZP),Y
323 
constant IYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010001011"; -- 0xD1 CMP (IND_ZP),Y
324 
constant IYCMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010001100"; -- 0xD1 CMP (IND_ZP),Y
325 
constant IYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110001000"; -- 0x31 AND (IND_ZP),Y
326 
constant IYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110001001"; -- 0x31 AND (IND_ZP),Y
327 
constant IYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110001010"; -- 0x31 AND (IND_ZP),Y
328 
constant IYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110001011"; -- 0x31 AND (IND_ZP),Y
329 
constant IYAND_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110001100"; -- 0x31 AND (IND_ZP),Y
330 
constant IYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010001000"; -- 0x11 ORA (IND_ZP),Y
331 
constant IYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010001001"; -- 0x11 ORA (IND_ZP),Y
332 
constant IYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010001010"; -- 0x11 ORA (IND_ZP),Y
333 
constant IYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010001011"; -- 0x11 ORA (IND_ZP),Y
334 
constant IYORA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010001100"; -- 0x11 ORA (IND_ZP),Y
335 
constant IYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010001000"; -- 0x51 EOR (IND_ZP),Y
336 
constant IYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010001001"; -- 0x51 EOR (IND_ZP),Y
337 
constant IYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010001010"; -- 0x51 EOR (IND_ZP),Y
338 
constant IYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010001011"; -- 0x51 EOR (IND_ZP),Y
339 
constant IYEOR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010001100"; -- 0x51 EOR (IND_ZP),Y
340 
 
341 
------------------------------------
342 
--          INDIRECT,X            --
343 
------------------------------------
344 
constant IXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100001000"; -- 0xA1 LDA (IND_ZP,X)
345 
constant IXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100001001"; -- 0xA1 LDA (IND_ZP,X)
346 
constant IXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10100001010"; -- 0xA1 LDA (IND_ZP,X)
347 
constant IXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10100001011"; -- 0xA1 LDA (IND_ZP,X)
348 
constant IXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000001000"; -- 0x81 STA (IND_ZP,X)
349 
constant IXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000001001"; -- 0x81 STA (IND_ZP,X)
350 
constant IXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000001010"; -- 0x81 STA (IND_ZP,X)
351 
constant IXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10000001011"; -- 0x81 STA (IND_ZP,X)
352 
constant IXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100001000"; -- 0x21 AND (IND_ZP,X)
353 
constant IXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100001001"; -- 0x21 AND (IND_ZP,X)
354 
constant IXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100001010"; -- 0x21 AND (IND_ZP,X)
355 
constant IXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100001011"; -- 0x21 AND (IND_ZP,X)
356 
constant IXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000001000"; -- 0x01 ORA (IND_ZP,X)
357 
constant IXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000001001"; -- 0x01 ORA (IND_ZP,X)
358 
constant IXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000001010"; -- 0x01 ORA (IND_ZP,X)
359 
constant IXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000001011"; -- 0x01 ORA (IND_ZP,X)
360 
constant IXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000001000"; -- 0x41 EOR (IND_ZP,X)
361 
constant IXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000001001"; -- 0x41 EOR (IND_ZP,X)
362 
constant IXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000001010"; -- 0x41 EOR (IND_ZP,X)
363 
constant IXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000001011"; -- 0x41 EOR (IND_ZP,X)
364 
constant IXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000001000"; -- 0xC1 CMP (IND_ZP,X)
365 
constant IXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000001001"; -- 0xC1 CMP (IND_ZP,X)
366 
constant IXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000001010"; -- 0xC1 CMP (IND_ZP,X)
367 
constant IXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000001011"; -- 0xC1 CMP (IND_ZP,X)
368 
constant IXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100001000"; -- 0x61 ADC (IND_ZP,X)
369 
constant IXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100001001"; -- 0x61 ADC (IND_ZP,X)
370 
constant IXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100001010"; -- 0x61 ADC (IND_ZP,X)
371 
constant IXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100001011"; -- 0x61 ADC (IND_ZP,X)
372 
constant IXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100001100"; -- 0x61 ADC (IND_ZP,X)
373 
constant IXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100001000"; -- 0xE1 SBC (IND_ZP,X)
374 
constant IXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100001001"; -- 0xE1 SBC (IND_ZP,X)
375 
constant IXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100001010"; -- 0xE1 SBC (IND_ZP,X)
376 
constant IXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100001011"; -- 0xE1 SBC (IND_ZP,X)
377 
constant IXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11100001100"; -- 0xE1 SBC (IND_ZP,X)
378 
constant IXJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111100000"; -- 0x7C JMP (IND,X)
379 
constant IXJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111100001"; -- 0x7C JMP (IND,X)
380 
constant IXJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111100010"; -- 0x7C JMP (IND,X)
381 
constant IXJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111100011"; -- 0x7C JMP (IND,X)
382 
constant IXJMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111100100"; -- 0x7C JMP (IND,X)
383 
constant IXJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111100000"; -- 0xFC JSR (IND,X)
384 
constant IXJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111100001"; -- 0xFC JSR (IND,X)
385 
constant IXJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111100010"; -- 0xFC JSR (IND,X)
386 
constant IXJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111100011"; -- 0xFC JSR (IND,X)
387 
constant IXJSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111100100"; -- 0xFC JSR (IND,X)
388 
constant IXJSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111100101"; -- 0xFC JSR (IND,X)
389 
 
390 
------------------------------------
391 
--            ABSOLUTE            --
392 
------------------------------------
393 
constant ABLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101101000"; -- 0xAD LDA ABS
394 
constant ABLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101101001"; -- 0xAD LDA ABS
395 
constant ABLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101101010"; -- 0xAD LDA ABS
396 
constant ABLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101110000"; -- 0xAE LDX ABS
397 
constant ABLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101110001"; -- 0xAE LDX ABS
398 
constant ABLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101110010"; -- 0xAE LDX ABS
399 
constant ABLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101100000"; -- 0xAC LDY ABS
400 
constant ABLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101100001"; -- 0xAC LDY ABS
401 
constant ABLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101100010"; -- 0xAC LDY ABS
402 
constant ABSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001101000"; -- 0x8D STA ABS
403 
constant ABSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001101001"; -- 0x8D STA ABS
404 
constant ABSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001101010"; -- 0x8D STA ABS
405 
constant ABSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001110000"; -- 0x8E STX ABS
406 
constant ABSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001110001"; -- 0x8E STX ABS
407 
constant ABSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001110010"; -- 0x8E STX ABS
408 
constant ABSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001100000"; -- 0x8C STY ABS
409 
constant ABSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001100001"; -- 0x8C STY ABS
410 
constant ABSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001100010"; -- 0x8C STY ABS
411 
constant ABSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011100000"; -- 0x9C STZ ABS
412 
constant ABSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011100001"; -- 0x9C STZ ABS
413 
constant ABSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011100010"; -- 0x9C STZ ABS
414 
constant ABADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101101000"; -- 0x6D ADC ABS
415 
constant ABADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101101001"; -- 0x6D ADC ABS
416 
constant ABADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101101010"; -- 0x6D ADC ABS
417 
constant ABADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101101011"; -- 0x6D ADC ABS
418 
constant ABSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101101000"; -- 0xED SBC ABS
419 
constant ABSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101101001"; -- 0xED SBC ABS
420 
constant ABSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101101010"; -- 0xED SBC ABS
421 
constant ABSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101101011"; -- 0xED SBC ABS
422 
constant ABORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001101000"; -- 0x0D ORA ABS
423 
constant ABORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001101001"; -- 0x0D ORA ABS
424 
constant ABORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001101010"; -- 0x0D ORA ABS
425 
constant ABAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101101000"; -- 0x2D AND ABS
426 
constant ABAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101101001"; -- 0x2D AND ABS
427 
constant ABAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101101010"; -- 0x2D AND ABS
428 
constant ABEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001101000"; -- 0x4D EOR ABS
429 
constant ABEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001101001"; -- 0x4D EOR ABS
430 
constant ABEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001101010"; -- 0x4D EOR ABS
431 
constant ABCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001101000"; -- 0xCD CMP ABS
432 
constant ABCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001101001"; -- 0xCD CMP ABS
433 
constant ABCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001101010"; -- 0xCD CMP ABS
434 
constant ABCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101100000"; -- 0xEC CPX ABS
435 
constant ABCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101100001"; -- 0xEC CPX ABS
436 
constant ABCPX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101100010"; -- 0xEC CPX ABS
437 
constant ABCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001100000"; -- 0xCC CPY ABS
438 
constant ABCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001100001"; -- 0xCC CPY ABS
439 
constant ABCPY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001100010"; -- 0xCC CPY ABS
440 
constant ABJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001100000"; -- 0x4C JMP ABS
441 
constant ABJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001100001"; -- 0x4C JMP ABS
442 
constant ABJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100000000"; -- 0x20 JSR ABS
443 
constant ABJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100000001"; -- 0x20 JSR ABS
444 
constant ABJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100000010"; -- 0x20 JSR ABS
445 
constant ABJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100000011"; -- 0x20 JSR ABS
446 
constant ABBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101100000"; -- 0x2C BIT ABS
447 
constant ABBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101100001"; -- 0x2C BIT ABS
448 
constant ABBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101100010"; -- 0x2C BIT ABS
449 
constant ABASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001110000"; -- 0x0E ASL ABS
450 
constant ABASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001110001"; -- 0x0E ASL ABS
451 
constant ABASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001110010"; -- 0x0E ASL ABS
452 
constant ABASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001110011"; -- 0x0E ASL ABS
453 
constant ABASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001110100"; -- 0x0E ASL ABS
454 
constant ABLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001110000"; -- 0x4E LSR ABS
455 
constant ABLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001110001"; -- 0x4E LSR ABS
456 
constant ABLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001110010"; -- 0x4E LSR ABS
457 
constant ABLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01001110011"; -- 0x4E LSR ABS
458 
constant ABLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01001110100"; -- 0x4E LSR ABS
459 
constant ABROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101110000"; -- 0x2E ROL ABS
460 
constant ABROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101110001"; -- 0x2E ROL ABS
461 
constant ABROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101110010"; -- 0x2E ROL ABS
462 
constant ABROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00101110011"; -- 0x2E ROL ABS
463 
constant ABROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00101110100"; -- 0x2E ROL ABS
464 
constant ABROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101110000"; -- 0x6E ROR ABS
465 
constant ABROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101110001"; -- 0x6E ROR ABS
466 
constant ABROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101110010"; -- 0x6E ROR ABS
467 
constant ABROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101110011"; -- 0x6E ROR ABS
468 
constant ABROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01101110100"; -- 0x6E ROR ABS
469 
constant ABINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101110000"; -- 0xEE INC ABS
470 
constant ABINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101110001"; -- 0xEE INC ABS
471 
constant ABINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101110010"; -- 0xEE INC ABS
472 
constant ABINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101110011"; -- 0xEE INC ABS
473 
constant ABINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11101110100"; -- 0xEE INC ABS
474 
constant ABDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001110000"; -- 0xCE DEC ABS
475 
constant ABDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001110001"; -- 0xCE DEC ABS
476 
constant ABDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001110010"; -- 0xCE DEC ABS
477 
constant ABDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11001110011"; -- 0xCE DEC ABS
478 
constant ABDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11001110100"; -- 0xCE DEC ABS
479 
constant ABTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001100000"; -- 0x0C TSB ABS
480 
constant ABTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001100001"; -- 0x0C TSB ABS
481 
constant ABTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001100010"; -- 0x0C TSB ABS
482 
constant ABTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001100011"; -- 0x0C TSB ABS
483 
constant ABTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001100100"; -- 0x0C TSB ABS
484 
constant ABTSB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00001100101"; -- 0x0C TSB ABS
485 
constant ABTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011100000"; -- 0x1C TRB ABS
486 
constant ABTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011100001"; -- 0x1C TRB ABS
487 
constant ABTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011100010"; -- 0x1C TRB ABS
488 
constant ABTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011100011"; -- 0x1C TRB ABS
489 
constant ABTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011100100"; -- 0x1C TRB ABS
490 
constant ABTRB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011100101"; -- 0x1C TRB ABS
491 
 
492 
------------------------------------
493 
--           ABSOLUTE,X           --
494 
------------------------------------
495 
constant AXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111101000"; -- 0xBD LDA ABS,X
496 
constant AXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111101001"; -- 0xBD LDA ABS,X
497 
constant AXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111101010"; -- 0xBD LDA ABS,X
498 
constant AXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111101011"; -- 0xBD LDA ABS,X
499 
constant AXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111100000"; -- 0xBC LDY ABS,X
500 
constant AXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111100001"; -- 0xBC LDY ABS,X
501 
constant AXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111100010"; -- 0xBC LDY ABS,X
502 
constant AXLDY_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111100011"; -- 0xBC LDY ABS,X
503 
constant AXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011101000"; -- 0x9D STA ABS,X
504 
constant AXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011101001"; -- 0x9D STA ABS,X
505 
constant AXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011101010"; -- 0x9D STA ABS,X
506 
constant AXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011101011"; -- 0x9D STA ABS,X
507 
constant AXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011110000"; -- 0x9E STZ ABS,X
508 
constant AXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011110001"; -- 0x9E STZ ABS,X
509 
constant AXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011110010"; -- 0x9E STZ ABS,X
510 
constant AXSTZ_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011110011"; -- 0x9E STZ ABS,X
511 
constant AXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111101000"; -- 0x7D ADC ABS,X
512 
constant AXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111101001"; -- 0x7D ADC ABS,X
513 
constant AXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111101010"; -- 0x7D ADC ABS,X
514 
constant AXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111101011"; -- 0x7D ADC ABS,X
515 
constant AXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111101100"; -- 0x7D ADC ABS,X
516 
constant AXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111101000"; -- 0xFD SBC ABS,X
517 
constant AXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111101001"; -- 0xFD SBC ABS,X
518 
constant AXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111101010"; -- 0xFD SBC ABS,X
519 
constant AXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111101011"; -- 0xFD SBC ABS,X
520 
constant AXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111101100"; -- 0xFD SBC ABS,X
521 
constant AXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011101000"; -- 0xDD CMP ABS,X
522 
constant AXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011101001"; -- 0xDD CMP ABS,X
523 
constant AXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011101010"; -- 0xDD CMP ABS,X
524 
constant AXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011101011"; -- 0xDD CMP ABS,X
525 
constant AXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111110000"; -- 0xFE INC ABS,X
526 
constant AXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111110001"; -- 0xFE INC ABS,X
527 
constant AXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111110010"; -- 0xFE INC ABS,X
528 
constant AXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111110011"; -- 0xFE INC ABS,X
529 
constant AXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111110100"; -- 0xFE INC ABS,X
530 
constant AXINC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111110101"; -- 0xFE INC ABS,X
531 
constant AXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011110000"; -- 0xDE DEC ABS,X
532 
constant AXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011110001"; -- 0xDE DEC ABS,X
533 
constant AXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011110010"; -- 0xDE DEC ABS,X
534 
constant AXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011110011"; -- 0xDE DEC ABS,X
535 
constant AXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11011110100"; -- 0xDE DEC ABS,X
536 
constant AXDEC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11011110101"; -- 0xDE DEC ABS,X
537 
constant AXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011110000"; -- 0x1E ASL ABS,X
538 
constant AXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011110001"; -- 0x1E ASL ABS,X
539 
constant AXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011110010"; -- 0x1E ASL ABS,X
540 
constant AXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011110011"; -- 0x1E ASL ABS,X
541 
constant AXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011110100"; -- 0x1E ASL ABS,X
542 
constant AXASL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011110101"; -- 0x1E ASL ABS,X
543 
constant AXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011110000"; -- 0x5E LSR ABS,X
544 
constant AXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011110001"; -- 0x5E LSR ABS,X
545 
constant AXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011110010"; -- 0x5E LSR ABS,X
546 
constant AXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011110011"; -- 0x5E LSR ABS,X
547 
constant AXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01011110100"; -- 0x5E LSR ABS,X
548 
constant AXLSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01011110101"; -- 0x5E LSR ABS,X
549 
constant AXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111110000"; -- 0x3E ROL ABS,X
550 
constant AXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111110001"; -- 0x3E ROL ABS,X
551 
constant AXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111110010"; -- 0x3E ROL ABS,X
552 
constant AXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111110011"; -- 0x3E ROL ABS,X
553 
constant AXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00111110100"; -- 0x3E ROL ABS,X
554 
constant AXROL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00111110101"; -- 0x3E ROL ABS,X
555 
constant AXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111110000"; -- 0x7E ROR ABS,X
556 
constant AXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111110001"; -- 0x7E ROR ABS,X
557 
constant AXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111110010"; -- 0x7E ROR ABS,X
558 
constant AXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111110011"; -- 0x7E ROR ABS,X
559 
constant AXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111110100"; -- 0x7E ROR ABS,X
560 
constant AXROR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01111110101"; -- 0x7E ROR ABS,X
561 
constant AXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111101000"; -- 0x3D AND ABS,X
562 
constant AXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111101001"; -- 0x3D AND ABS,X
563 
constant AXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111101010"; -- 0x3D AND ABS,X
564 
constant AXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111101011"; -- 0x3D AND ABS,X
565 
constant AXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011101000"; -- 0x1D ORA ABS,X
566 
constant AXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011101001"; -- 0x1D ORA ABS,X
567 
constant AXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011101010"; -- 0x1D ORA ABS,X
568 
constant AXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011101011"; -- 0x1D ORA ABS,X
569 
constant AXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011101000"; -- 0x5D EOR ABS,X
570 
constant AXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011101001"; -- 0x5D EOR ABS,X
571 
constant AXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011101010"; -- 0x5D EOR ABS,X
572 
constant AXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011101011"; -- 0x5D EOR ABS,X
573 
constant AXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111100000"; -- 0x3C BIT ABS,X
574 
constant AXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111100001"; -- 0x3C BIT ABS,X
575 
constant AXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111100010"; -- 0x3C BIT ABS,X
576 
constant AXBIT_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111100011"; -- 0x3C BIT ABS,X
577 
 
578 
------------------------------------
579 
--           ABSOLUTE,Y           --
580 
------------------------------------
581 
constant AYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111001000"; -- 0xB9 LDA ABS,Y
582 
constant AYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111001001"; -- 0xB9 LDA ABS,Y
583 
constant AYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111001010"; -- 0xB9 LDA ABS,Y
584 
constant AYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111001011"; -- 0xB9 LDA ABS,Y
585 
constant AYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111110000"; -- 0xBE LDX ABS,Y
586 
constant AYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111110001"; -- 0xBE LDX ABS,Y
587 
constant AYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111110010"; -- 0xBE LDX ABS,Y
588 
constant AYLDX_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111110011"; -- 0xBE LDX ABS,Y
589 
constant AYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011001000"; -- 0x99 STA ABS,Y
590 
constant AYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011001001"; -- 0x99 STA ABS,Y
591 
constant AYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011001010"; -- 0x99 STA ABS,Y
592 
constant AYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011001011"; -- 0x99 STA ABS,Y
593 
constant AYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111001000"; -- 0x79 ADC ABS,Y
594 
constant AYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111001001"; -- 0x79 ADC ABS,Y
595 
constant AYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111001010"; -- 0x79 ADC ABS,Y
596 
constant AYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111001011"; -- 0x79 ADC ABS,Y
597 
constant AYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111001100"; -- 0x79 ADC ABS,Y
598 
constant AYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111001000"; -- 0xF9 SBC ABS,Y
599 
constant AYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111001001"; -- 0xF9 SBC ABS,Y
600 
constant AYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111001010"; -- 0xF9 SBC ABS,Y
601 
constant AYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111001011"; -- 0xF9 SBC ABS,Y
602 
constant AYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111001100"; -- 0xF9 SBC ABS,Y
603 
constant AYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011001000"; -- 0xD9 CMP ABS,Y
604 
constant AYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011001001"; -- 0xD9 CMP ABS,Y
605 
constant AYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011001010"; -- 0xD9 CMP ABS,Y
606 
constant AYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011001011"; -- 0xD9 CMP ABS,Y
607 
constant AYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011001000"; -- 0x19 ORA ABS,Y
608 
constant AYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011001001"; -- 0x19 ORA ABS,Y
609 
constant AYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011001010"; -- 0x19 ORA ABS,Y
610 
constant AYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011001011"; -- 0x19 ORA ABS,Y
611 
constant AYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111001000"; -- 0x39 AND ABS,Y
612 
constant AYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111001001"; -- 0x39 AND ABS,Y
613 
constant AYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111001010"; -- 0x39 AND ABS,Y
614 
constant AYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111001011"; -- 0x39 AND ABS,Y
615 
constant AYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011001000"; -- 0x59 EOR ABS,Y
616 
constant AYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011001001"; -- 0x59 EOR ABS,Y
617 
constant AYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011001010"; -- 0x59 EOR ABS,Y
618 
constant AYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011001011"; -- 0x59 EOR ABS,Y
619 
 
620 
------------------------------------
621 
--           RELATIVE             --
622 
------------------------------------
623 
constant   BRA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000000000"; -- 0x80 BRA
624 
constant   BRA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000000001"; -- 0x80 BRA
625 
constant   BRA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000000010"; -- 0x80 BRA
626 
constant   BCC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010000000"; -- 0x90 BCC
627 
constant   BCC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010000001"; -- 0x90 BCC
628 
constant   BCC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010000010"; -- 0x90 BCC
629 
constant   BCS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110000000"; -- 0xB0 BCS
630 
constant   BCS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110000001"; -- 0xB0 BCS
631 
constant   BCS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110000010"; -- 0xB0 BCS
632 
constant   BEQ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110000000"; -- 0xF0 BEQ
633 
constant   BEQ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110000001"; -- 0xF0 BEQ
634 
constant   BEQ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110000010"; -- 0xF0 BEQ
635 
constant   BNE_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010000000"; -- 0xD0 BNE
636 
constant   BNE_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010000001"; -- 0xD0 BNE
637 
constant   BNE_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010000010"; -- 0xD0 BNE
638 
constant   BPL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010000000"; -- 0x10 BPL
639 
constant   BPL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010000001"; -- 0x10 BPL
640 
constant   BPL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010000010"; -- 0x10 BPL
641 
constant   BMI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110000000"; -- 0x30 BMI
642 
constant   BMI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110000001"; -- 0x30 BMI
643 
constant   BMI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110000010"; -- 0x30 BMI
644 
constant   BVC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010000000"; -- 0x50 BVC
645 
constant   BVC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010000001"; -- 0x50 BVC
646 
constant   BVC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010000010"; -- 0x50 BVC
647 
constant   BVS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110000000"; -- 0x70 BVS
648 
constant   BVS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110000001"; -- 0x70 BVS
649 
constant   BVS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110000010"; -- 0x70 BVS
650 
 
651 
-- ALU microcode
652 
constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- ALU no operation
653 
constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- ALU add with carry
654 
constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- ALU sub with borrow
655 
constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- ALU and
656 
constant  OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- ALU or
657 
constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- ALU xor
658 
constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- ALU increment by 1
659 
constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- ALU decrement by 1
660 
constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- ALU bit shift left
661 
constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- ALU bit shift right
662 
constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- ALU bit rotation left
663 
constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- ALU bit rotation right
664 
constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- ALU add without carry
665 
constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- ALU bit test
666 
constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- ALU add without carry (used for DAA decimal adjustement)
667 
constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- ALU sub without borrow (used for DAA decimal adjustement)
668 
constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- SBC without borrow in (used for CMP instruction)
669 
constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- test and set bit
670 
constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- test and reset bit
671 
 
672 
-- PCR microcode
673 
constant NOP_PC: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- PC no operation
674 
constant LSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- PC load lsb
675 
constant MSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- PC load msb
676 
constant INC_PC: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- PC increment by 1
677 
constant LOD_PC: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- PC load lsb\msb
678 
constant ADJ_PC: STD_LOGIC_VECTOR(2 downto 0) := "101"; -- PC msb adjustement (+/- by 1)
679 
 
680 
-- MPR microcode
681 
constant NOP_M: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
682 
constant LSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- load lsb
683 
constant MSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- load msb
684 
constant INC_M: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- increment LSB
685 
constant VEC_M: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- load vector
686 
constant ZPL_M: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- load ZEROPAGE
687 
constant ALL_M: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- load all 16 bit register
688 
constant ICC_M: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- increment MSB with carry
689 
constant INM_M: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- increment MSB/LSB
690 
 
691 
-- address multiplexer microcode
692 
constant ADPC: STD_LOGIC_VECTOR(1 downto 0) := "00";    -- select PC
693 
constant ADMP: STD_LOGIC_VECTOR(1 downto 0) := "01";    -- select MP
694 
constant ADSP: STD_LOGIC_VECTOR(1 downto 0) := "10";    -- select MP/SP
695 
constant ADNP: STD_LOGIC_VECTOR(1 downto 0) := "00";    -- no operation
696 
 
697 
-- PR microcode
698 
constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
699 
constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
700 
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
701 
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
702 
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
703 
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
704 
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
705 
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
706 
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
707 
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
708 
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
709 
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
710 
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
711 
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
712 
 
713 
-- register operation microcode REGOP
714 
constant NOP_R: STD_LOGIC_VECTOR(3 downto 0) := "0000";  -- no operation
715 
constant ALD_R: STD_LOGIC_VECTOR(3 downto 0) := "0001";  -- register A load
716 
constant XLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0010";  -- register X load
717 
constant YLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0011";  -- register Y load
718 
constant ZLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0100";  -- register Z load
719 
constant OLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0101";  -- register O load
720 
constant SLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0110";  -- register S load lsb
721 
constant SLM_R: STD_LOGIC_VECTOR(3 downto 0) := "0111";  -- register S load msb
722 
constant SUP_R: STD_LOGIC_VECTOR(3 downto 0) := "1000";  -- register S increment by 1
723 
constant SDW_R: STD_LOGIC_VECTOR(3 downto 0) := "1001";  -- register S decrement by 1
724 
constant SAU_R: STD_LOGIC_VECTOR(3 downto 0) := "1010";  -- register A load/register S increment by 1
725 
constant SXU_R: STD_LOGIC_VECTOR(3 downto 0) := "1011";  -- register X load/register S increment by 1
726 
constant SYU_R: STD_LOGIC_VECTOR(3 downto 0) := "1100";  -- register Y load/register S increment by 1
727 
constant SZU_R: STD_LOGIC_VECTOR(3 downto 0) := "1101";  -- register Z load/register S increment by 1
728 
 
729 
-- register multiplexer microcode RSEL (ALU operand #1)
730 
constant EXT_O: STD_LOGIC_VECTOR(3 downto 0) := "0000";  -- external data bus
731 
constant ARD_O: STD_LOGIC_VECTOR(3 downto 0) := "0001";  -- register A select
732 
constant XRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0010";  -- register X select
733 
constant YRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0011";  -- register Y select
734 
constant SRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0100";  -- register S lsb select
735 
constant SRM_O: STD_LOGIC_VECTOR(3 downto 0) := "0101";  -- register S msb select
736 
constant PRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0110";  -- register P select
737 
constant PLR_O: STD_LOGIC_VECTOR(3 downto 0) := "0111";  -- register PCL select
738 
constant PHR_O: STD_LOGIC_VECTOR(3 downto 0) := "1000";  -- register PCH select
739 
constant ORD_O: STD_LOGIC_VECTOR(3 downto 0) := "1001";  -- register O select
740 
constant Z00_O: STD_LOGIC_VECTOR(3 downto 0) := "1010";  -- select (all zero output)
741 
constant ZRD_O: STD_LOGIC_VECTOR(3 downto 0) := "1011";  -- register Z select (all zero output)
742 
 
743 
-- data multiplexer microcode DMUX (ALU operand #2)
744 
constant NOP_D: STD_LOGIC_VECTOR(1 downto 0) := "00";
745 
constant ORD_D: STD_LOGIC_VECTOR(1 downto 0) := "01";
746 
constant EXT_D: STD_LOGIC_VECTOR(1 downto 0) := "10";
747 
constant BCD_D: STD_LOGIC_VECTOR(1 downto 0) := "11";
748 
 
749 
-- read/write control
750 
constant   RDE: STD_LOGIC_VECTOR(1 downto 0) := "11";    -- data bus read
751 
constant   WRE: STD_LOGIC_VECTOR(1 downto 0) := "10";    -- data bus write (combinatorial mode)
752 
constant   WRL: STD_LOGIC_VECTOR(1 downto 0) := "01";    -- data bus write (registered mode)
753 
 
754 
begin
755 
  process(a)
756 
  begin
757 
  -- The PLA is arranged like an ROM, there are an address input "a" and an data output "q". The address of PLA is 11 bit wide
758 
  -- and composed in this way:
759 
  --
760 
  -- ----  CPU OPCODE   ----  - MPC -
761 
  -- |                     |  |     |
762 
  -- |                     |  |     |
763 
  --  X--X--X--X--X--X--X--X--Y--Y--Y
764 
  -- 10-09-08-07-06-05-04-03-02-01-00
765 
  --
766 
  -- the bits (10-3) (X field) is formed by CPU instruction opcode
767 
  -- the bits (2-0) (Y field) is formed by the three bit wide microinstruction program counter (MPC)
768 
  -- The MPC field is cleared at each opcode fetch by FSM and since it's three bit wide there are
769 
  -- an maximum of eight microinstructions available per opcode
770 
  --
771 
  -- The bits 10-3 of PLA address serves to select the microcode group of a related CPU opcode
772 
  -- and they are stable for all instruction execution time, instead the remaining three bit 2-0 (MPC field) of PLA address
773 
  -- increment at each clock in order to address the next microcode instructions.
774 
  -- microcode assembly:
775 
  -- Due the particulary pipeline structure of this CPU, all microinstructions have an extra cycle hidden on fetch
776 
  -- of the next opcode instruction and normally this extra cycle is coded as "NOP" (see the last line  "when  others =>...").
777 
  -- However there are some instructions where this extra cycle is used for some functions like decimal adjustments etc of
778 
  -- ADC and SBC instructions (see DAA and DAS).
779 
  --
780 
  -- Microcode fields:
781 
  --
782 
  --                          DMUX: ALU operand #2 multiplexer
783 
  --                          |       AI: effective address is indexed (X or Y)
784 
  --                          |       |   VP: vector pull
785 
  --                          |       |   |   BR: branch opcode
786 
  --                          |       |   |   |   EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
787 
  --                          |       |   |   |   |   W: read/write control
788 
  --                          |       |   |   |   |   |    CLI: clear interrupt request
789 
  --                          |       |   |   |   |   |    |    PD: PC/MP address output multiplexer select
790 
  --                          |       |   |   |   |   |    |    |      PCR: register PC (program counter)
791 
  --                          |       |   |   |   |   |    |    |      |        MPR: register MP (memory pointer)
792 
  --                          |       |   |   |   |   |    |    |      |        |       P_OP: register P set/reset bit
793 
  --                          |       |   |   |   |   |    |    |      |        |       |       ALUOP: ALU operation
794 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       REGOP: registers load/increment/decrement etc.
795 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       RSEL: registers output multiplexer select
796 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       |
797 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       |
798 
    case a is              -- DMUX    AI  VP  BR  EI  W    CLI  PD     PCR      MPR     P_OP    ALUOP   REGOP   RSEL
799 
      ------------------------------------
800 
      --            IMPLIED             --
801 
      ------------------------------------
802 
      -- BRK
803 
      when    BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- NOPs
804 
      when    BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1
805 
      when    BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1
806 
      when    BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ZRD_O; -- Z->S; SP-1; EI
807 
      when    BRK_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & SDW_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD
808 
      when    BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP
809 
      when    BRK_OP6 => q <= ORD_D &'0'&'1'&'0'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP
810 
 
811 
      -- NOP
812 
      when    NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
813 
 
814 
      -- CLC
815 
      when    CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI
816 
 
817 
      -- SEC
818 
      when    SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI
819 
 
820 
      -- CLI
821 
      when    CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI
822 
 
823 
      -- SEI
824 
      when    SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI
825 
 
826 
      -- CLV
827 
      when    CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI
828 
 
829 
      -- CLD
830 
      when    CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI
831 
 
832 
      -- SED
833 
      when    SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI
834 
 
835 
      -- TAX
836 
      when    TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & ARD_O; -- A->X; EI
837 
 
838 
      -- TXA
839 
      when    TXA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & XRD_O; -- X->A; EI
840 
 
841 
      -- TAY
842 
      when    TAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & ARD_O; -- A->Y; EI
843 
 
844 
      -- TYA
845 
      when    TYA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & YRD_O; -- Y->A; EI
846 
 
847 
      -- TXY
848 
      when    TXY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & XRD_O; -- X->Y; EI
849 
 
850 
      -- TYX
851 
      when    TYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & YRD_O; -- Y->X; EI
852 
 
853 
      -- TAZ
854 
      when    TAZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ZLD_R & ARD_O; -- A->Z; EI
855 
 
856 
      -- TZA
857 
      when    TZA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & ZRD_O; -- Z->A; EI
858 
 
859 
      -- TXS
860 
      when    TXS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S; EI
861 
 
862 
      -- TSX
863 
      when    TSX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S->X; EI
864 
 
865 
      -- INC A
866 
      when    INC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & ALD_R & ARD_O; -- A+1; EI
867 
 
868 
      -- DEC A
869 
      when    DEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & ALD_R & ARD_O; -- A-1; EI
870 
 
871 
      -- INX
872 
      when    INX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & XLD_R & XRD_O; -- X+1; EI
873 
 
874 
      -- DEX
875 
      when    DEX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & XLD_R & XRD_O; -- X-1; EI
876 
 
877 
      -- INY
878 
      when    INY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & YLD_R & YRD_O; -- Y+1; EI
879 
 
880 
      -- DEY
881 
      when    DEY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & YLD_R & YRD_O; -- Y-1; EI
882 
 
883 
      -- PHP
884 
      when    PHP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; EI
885 
 
886 
      -- PHA
887 
      when    PHA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1; EI
888 
 
889 
      -- PHX
890 
      when    PHX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; EI
891 
 
892 
      -- PHY
893 
      when    PHY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- X->S; SP-1; EI
894 
 
895 
      -- PHR
896 
      when    PHR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1;
897 
      when    PHR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1;
898 
      when    PHR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y->S; SP-1; EI
899 
 
900 
      -- PLP
901 
      when    PLP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
902 
      when    PLP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & NOP_R & EXT_O; -- S->P; EI
903 
 
904 
      -- PLA
905 
      when    PLA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
906 
      when    PLA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
907 
 
908 
      -- PLX
909 
      when    PLX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
910 
      when    PLX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- S->X; EI
911 
 
912 
      -- PLY
913 
      when    PLY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
914 
      when    PLY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- S->Y; EI
915 
 
916 
      -- PLR
917 
      when    PLR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
918 
      when    PLR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y;
919 
      when    PLR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X;
920 
      when    PLR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
921 
 
922 
      -- RTI
923 
      when    RTI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; MP=01XX (STACK)
924 
      when    RTI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; MEM->P; SP +1
925 
      when    RTI_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SZU_R & EXT_O; -- S->Z;
926 
      when    RTI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB PC->O; SP +1;
927 
      when    RTI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; SP +1;
928 
      when    RTI_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; MSB->MP; EI
929 
 
930 
      -- RTS
931 
      when    RTS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1
932 
      when    RTS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O;
933 
      when    RTS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1;
934 
      when    RTS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC
935 
      when    RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI
936 
 
937 
      -- ASL (A)
938 
      when    ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHL_A & ALD_R & ARD_O; -- A SHIFT LEFT; EI
939 
 
940 
      -- LSR (A)
941 
      when    LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHR_A & ALD_R & ARD_O; -- A SHIFT RIGHT; EI
942 
 
943 
      -- ROL (A)
944 
      when    ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROL_A & ALD_R & ARD_O; -- A ROTATE LEFT; EI
945 
 
946 
      -- ROR (A)
947 
      when    ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROR_A & ALD_R & ARD_O; -- A ROTATE RIGHT; EI
948 
 
949 
      -- XYX
950 
      when    XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
951 
      when    XYX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & YRD_O; -- Y->X;
952 
      when    XYX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ORD_O; -- O->Y; EI
953 
 
954 
      -- XAX
955 
      when    XAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
956 
      when    XAX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & ARD_O; -- A->X;
957 
      when    XAX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
958 
 
959 
      -- XAY
960 
      when    XAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & YRD_O; -- Y->O;
961 
      when    XAY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ARD_O; -- A->Y;
962 
      when    XAY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
963 
 
964 
      -- ISP
965 
      when    ISP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S lsb;
966 
      when    ISP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLM_R & ARD_O; -- A->S msb; EI
967 
 
968 
      -- TSP
969 
      when    TSP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S lsb ->X;
970 
      when    TSP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & SRM_O; -- S msb ->A; EI
971 
 
972 
 
973 
      ------------------------------------
974 
      --           IMMEDIATE            --
975 
      ------------------------------------
976 
      -- LDA #xx
977 
      when  IMLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MEM->A; PC +1; EI
978 
 
979 
      -- LDX #xx
980 
      when  IMLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MEM->X; PC +1; EI
981 
 
982 
      -- LDY #yy
983 
      when  IMLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MEM->Y; PC +1; EI
984 
 
985 
      -- ADC #xx (immediate)
986 
      when  IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; PC +1; EI
987 
      when  IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
988 
 
989 
      -- SBC #xx (immediate)
990 
      when  IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; PC +1; EI
991 
      when  IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
992 
 
993 
      -- CMP #xx (immediate)
994 
      when  IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI
995 
 
996 
      -- CPX #xx (immediate)
997 
      when  IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI
998 
 
999 
      -- CPY #xx (immediate)
1000 
      when  IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI
1001 
 
1002 
      -- AND #xx (immediate)
1003 
      when  IMAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A AND MEM -> A; PC +1;
1004 
 
1005 
      -- ORA #xx (immediate)
1006 
      when  IMORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A OR MEM -> A; PC +1;
1007 
 
1008 
      -- EOR #xx (immediate)
1009 
      when  IMEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A XOR MEM -> A; PC +1;
1010 
 
1011 
      -- BIT #xx (immediate)
1012 
      when  IMBRK_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & LDZ_P & BIT_A & NOP_R & ARD_O; -- A AND MEM; PC +1;
1013 
 
1014 
 
1015 
      ------------------------------------
1016 
      --           ZERO PAGE            --
1017 
      ------------------------------------
1018 
      -- LDA $xx (zero page)
1019 
      when  ZPLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1020 
      when  ZPLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1; EI
1021 
 
1022 
      -- LDX $xx (zero page)
1023 
      when  ZPLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1024 
      when  ZPLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1; EI
1025 
 
1026 
      -- LDY $xx (zero page)
1027 
      when  ZPLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1028 
      when  ZPLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI
1029 
 
1030 
      -- STA $xx (zero page)
1031 
      when  ZPSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1032 
      when  ZPSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1; EI
1033 
 
1034 
      -- STX $xx (zero page)
1035 
      when  ZPSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1036 
      when  ZPSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1; EI
1037 
 
1038 
      -- STY $xx (zero page)
1039 
      when  ZPSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1040 
      when  ZPSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1; EI
1041 
 
1042 
      -- STZ $xx (zero page)
1043 
      when  ZPSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1044 
      when  ZPSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1; EI
1045 
 
1046 
      -- ADC $xx (zero page)
1047 
      when  ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1048 
      when  ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
1049 
      when  ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1050 
 
1051 
      -- SBC $xx (zero page)
1052 
      when  ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1053 
      when  ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
1054 
      when  ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1055 
 
1056 
      -- CMP $xx (zeropage)
1057 
      when  ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1058 
      when  ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
1059 
 
1060 
      -- CPX $xx (zeropage)
1061 
      when  ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1062 
      when  ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI
1063 
 
1064 
      -- CPY $xx (zeropage)
1065 
      when  ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1066 
      when  ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI
1067 
 
1068 
      -- AND $xx (zeropage)
1069 
      when  ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1070 
      when  ZPAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM;  EI
1071 
 
1072 
      -- ORA $xx (zeropage)
1073 
      when  ZPORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1074 
      when  ZPORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM;  EI
1075 
 
1076 
      -- EOR $xx (zeropage)
1077 
      when  ZPEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1078 
      when  ZPEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM;  EI
1079 
 
1080 
      -- BIT $xx (zero page)
1081 
      when  ZPBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1082 
      when  ZPBIT_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1; EI
1083 
 
1084 
      -- ASL $xx (zero page)
1085 
      when  ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1086 
      when  ZPASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1087 
      when  ZPASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1088 
      when  ZPASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1089 
 
1090 
      -- LSR $xx (zero page)
1091 
      when  ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1092 
      when  ZPLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1093 
      when  ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1094 
      when  ZPLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1095 
 
1096 
      -- ROL $xx (zero page)
1097 
      when  ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1098 
      when  ZPROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1099 
      when  ZPROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1100 
      when  ZPROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1101 
 
1102 
      -- ROR $xx (zero page)
1103 
      when  ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1104 
      when  ZPROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1105 
      when  ZPROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1106 
      when  ZPROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1107 
 
1108 
      -- INC $xx (zero page)
1109 
      when  ZPINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1110 
      when  ZPINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1111 
      when  ZPINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1112 
      when  ZPINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1113 
 
1114 
      -- DEC $xx (zero page)
1115 
      when  ZPDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1116 
      when  ZPDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1117 
      when  ZPDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1118 
      when  ZPDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1119 
 
1120 
      -- TSB $xx (zero page)
1121 
      when  ZPTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1122 
      when  ZPTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1123 
      when  ZPTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1124 
      when  ZPTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O -> O
1125 
      when  ZPTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1126 
 
1127 
      -- TRB $xx (zero page)
1128 
      when  ZPTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1129 
      when  ZPTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1130 
      when  ZPTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1131 
      when  ZPTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O -> O
1132 
      when  ZPTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1133 
 
1134 
      ------------------------------------
1135 
      --          ZERO PAGE,X           --
1136 
      ------------------------------------
1137 
      -- LDA $xx,X (zero page indexed)
1138 
      when  ZXLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1139 
      when  ZXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1140 
      when  ZXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1141 
 
1142 
      -- LDY $xx,X (zero page indexed)
1143 
      when  ZXLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1144 
      when  ZXLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1145 
      when  ZXLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
1146 
 
1147 
      -- STA $xx,X (zero page indexed)
1148 
      when  ZXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1149 
      when  ZXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1150 
      when  ZXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1151 
 
1152 
      -- STY $xx,X (zero page indexed)
1153 
      when  ZXSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1154 
      when  ZXSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1155 
      when  ZXSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; EI
1156 
 
1157 
      -- STZ $xx,X (zero page indexed)
1158 
      when  ZXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1159 
      when  ZXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1160 
      when  ZXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; X->MEM; EI
1161 
 
1162 
      -- ADC $xx,X (zero page indexed)
1163 
      when  ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1164 
      when  ZXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1165 
      when  ZXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
1166 
      when  ZXADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); EI
1167 
 
1168 
      -- SBC $xx,X (zero page indexed)
1169 
      when  ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1170 
      when  ZXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1171 
      when  ZXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
1172 
      when  ZXSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); EI
1173 
 
1174 
      -- CMP $xx,X (zero page indexed)
1175 
      when  ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1176 
      when  ZXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1177 
      when  ZXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
1178 
 
1179 
      -- AND $xx,X (zero page indexed)
1180 
      when  ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1181 
      when  ZXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1182 
      when  ZXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM;  EI
1183 
 
1184 
      -- ORA $xx,X (zero page indexed)
1185 
      when  ZXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1186 
      when  ZXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1187 
      when  ZXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM;  EI
1188 
 
1189 
      -- EOR $xx,X (zero page indexed)
1190 
      when  ZXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1191 
      when  ZXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1192 
      when  ZXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM;  EI
1193 
 
1194 
      -- ASL $xx,X (zero page indexed)
1195 
      when  ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1196 
      when  ZXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X PC+1;
1197 
      when  ZXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1198 
      when  ZXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1199 
      when  ZXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1200 
 
1201 
      -- LSR $xx,X (zero page indexed)
1202 
      when  ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP
1203 
      when  ZXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1204 
      when  ZXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1205 
      when  ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1206 
      when  ZXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1207 
 
1208 
      -- ROL $xx,X (zero page indexed)
1209 
      when  ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1210 
      when  ZXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1211 
      when  ZXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1212 
      when  ZXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1213 
      when  ZXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1214 
 
1215 
      -- ROR $xx,X (zero page indexed)
1216 
      when  ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1217 
      when  ZXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1218 
      when  ZXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1219 
      when  ZXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1220 
      when  ZXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1221 
 
1222 
      -- INC $xx,X (zero page indexed)
1223 
      when  ZXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1224 
      when  ZXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1225 
      when  ZXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1226 
      when  ZXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1227 
      when  ZXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1228 
 
1229 
      -- DEC $xx,X (zero page indexed)
1230 
      when  ZXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1231 
      when  ZXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1232 
      when  ZXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1233 
      when  ZXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1234 
      when  ZXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1235 
 
1236 
      -- BIT $xx,X (zero page indexed)
1237 
      when  ZXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1238 
      when  ZXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1239 
      when  ZXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A = A AND MEM;  EI
1240 
 
1241 
      ------------------------------------
1242 
      --          ZERO PAGE,Y           --
1243 
      ------------------------------------
1244 
      -- LDX $xx,Y (zero page indexed)
1245 
      when  ZYLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1246 
      when  ZYLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
1247 
      when  ZYLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
1248 
 
1249 
      -- STX $xx,Y (zero page indexed)
1250 
      when  ZYSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1251 
      when  ZYSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
1252 
      when  ZYSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; EI
1253 
 
1254 
      ------------------------------------
1255 
      --           INDIRECT             --
1256 
      ------------------------------------
1257 
      -- JMP ($xxxx) (indirect)
1258 
      when  INJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1259 
      when  INJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1260 
      when  INJMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1
1261 
      when  INJMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC; O->PC; EI
1262 
 
1263 
      ------------------------------------
1264 
      --          INDIRECT,Y            --
1265 
      ------------------------------------
1266 
      -- LDA ($xx),Y (zeropage - indirect - indexed)
1267 
      when  IYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1268 
      when  IYLDA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1269 
      when  IYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1270 
      when  IYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- O->MP; (LSB POINTER)
1271 
      when  IYLDA_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1272 
 
1273 
      -- STA ($xx),Y (zeropage - indirect - indexed)
1274 
      when  IYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1275 
      when  IYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1276 
      when  IYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1277 
      when  IYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O->MP; (LSB POINTER)
1278 
      when  IYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1279 
 
1280 
      -- ADC ($xx),Y (zeropage - indirect - indexed)
1281 
      when  IYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1282 
      when  IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1283 
      when  IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1284 
      when  IYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1285 
      when  IYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1286 
      when  IYADC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1287 
 
1288 
      -- SBC ($xx),Y (zeropage - indirect - indexed)
1289 
      when  IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1290 
      when  IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1291 
      when  IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1292 
      when  IYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1293 
      when  IYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1294 
      when  IYSBC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAS); PC +1; EI
1295 
 
1296 
      -- CMP ($xx),Y (zeropage - indirect - indexed)
1297 
      when  IYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1298 
      when  IYCMP_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1299 
      when  IYCMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1300 
      when  IYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1301 
      when  IYCMP_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM;  A-MEM; EI
1302 
 
1303 
      -- AND ($xx),Y (zeropage - indirect - indexed)
1304 
      when  IYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1305 
      when  IYAND_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1306 
      when  IYAND_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1307 
      when  IYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1308 
      when  IYAND_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM; EI
1309 
 
1310 
      -- ORA ($xx),Y (zeropage - indirect - indexed)
1311 
      when  IYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1312 
      when  IYORA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1313 
      when  IYORA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1314 
      when  IYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1315 
      when  IYORA_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM; EI
1316 
 
1317 
      -- EOR ($xx),Y (zeropage - indirect - indexed)
1318 
      when  IYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1319 
      when  IYEOR_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1320 
      when  IYEOR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1321 
      when  IYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1322 
      when  IYEOR_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM; EI
1323 
 
1324 
      ------------------------------------
1325 
      --          INDIRECT,X            --
1326 
      ------------------------------------
1327 
      -- LDA ($xx,X) (zero page - indexed - indirect)
1328 
      when  IXLDA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1329 
      when  IXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1330 
      when  IXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1331 
      when  IXLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI=1
1332 
 
1333 
      -- STA ($xx,X) (zero page - indexed - indirect)
1334 
      when  IXSTA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1335 
      when  IXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1336 
      when  IXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1337 
      when  IXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- A->MEM; EI=1
1338 
 
1339 
      -- AND ($xx,X) (zero page - indexed - indirect)
1340 
      when  IXAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1341 
      when  IXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1342 
      when  IXAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1343 
      when  IXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; A=A AND MEM; EI=1
1344 
 
1345 
      -- ORA ($xx,X) (zero page - indexed - indirect)
1346 
      when  IXORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1347 
      when  IXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1348 
      when  IXORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1349 
      when  IXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; A=A OR MEM; EI=1
1350 
 
1351 
      -- EOR ($xx,X) (zero page - indexed - indirect)
1352 
      when  IXEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1353 
      when  IXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1354 
      when  IXEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1355 
      when  IXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1356 
 
1357 
      -- ADC ($xx,X) (zero page - indexed - indirect)
1358 
      when  IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1359 
      when  IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1360 
      when  IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1361 
      when  IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1362 
      when  IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1363 
 
1364 
      -- SBC ($xx,X) (zero page - indexed - indirect)
1365 
      when  IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1366 
      when  IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1367 
      when  IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1368 
      when  IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1369 
      when  IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1370 
 
1371 
      -- CMP ($xx,X) (zero page - indexed - indirect)
1372 
      when  IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1373 
      when  IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1374 
      when  IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1375 
      when  IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1376 
 
1377 
      -- JMP ($xxxx,X) (absolute indexed - indirect)
1378 
      when  IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1379 
      when  IXJMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1380 
      when  IXJMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1381 
      when  IXJMP_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1382 
      when  IXJMP_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1383 
 
1384 
      -- JSR ($xxxx,X) (absolute indexed - indirect)
1385 
      when  IXJSR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1386 
      when  IXJSR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
1387 
      when  IXJSR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
1388 
      when  IXJSR_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1389 
      when  IXJSR_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1390 
      when  IXJSR_OP5 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1391 
 
1392 
      ------------------------------------
1393 
      --           ABSOLUTE             --
1394 
      ------------------------------------
1395 
      -- LDA $xxxx (absolute)
1396 
      when  ABLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1397 
      when  ABLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1398 
      when  ABLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1
1399 
 
1400 
      -- LDX $xxxx (absolute)
1401 
      when  ABLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1402 
      when  ABLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1403 
      when  ABLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1
1404 
 
1405 
      -- LDY $xxxx (absolute)
1406 
      when  ABLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1407 
      when  ABLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1408 
      when  ABLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1
1409 
 
1410 
      -- STA $xxxx (absolute)
1411 
      when  ABSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1412 
      when  ABSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1413 
      when  ABSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1
1414 
 
1415 
      -- STX $xxxx (absolute)
1416 
      when  ABSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1417 
      when  ABSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1418 
      when  ABSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1
1419 
 
1420 
      -- STY $xxxx (absolute)
1421 
      when  ABSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1422 
      when  ABSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1423 
      when  ABSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1
1424 
 
1425 
      -- STZ $xxxx (absolute)
1426 
      when  ABSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1427 
      when  ABSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1428 
      when  ABSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1
1429 
 
1430 
      -- JMP $xxxx (absolute)
1431 
      when  ABJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
1432 
      when  ABJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1433 
 
1434 
      -- JSR $xxxx (absolute)
1435 
      when  ABJSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
1436 
      when  ABJSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
1437 
      when  ABJSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
1438 
      when  ABJSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1439 
 
1440 
      -- BIT $xxxx (absolute)
1441 
      when  ABBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1442 
      when  ABBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1443 
      when  ABBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1
1444 
 
1445 
      -- ADC $xxxx (absolute)
1446 
      when  ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1447 
      when  ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1448 
      when  ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; EI
1449 
      when  ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1450 
 
1451 
      -- SBC $xxxx (absolute)
1452 
      when  ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1453 
      when  ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1454 
      when  ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; EI
1455 
      when  ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
1456 
 
1457 
      -- CMP $xxxx (absolute)
1458 
      when  ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1459 
      when  ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1460 
      when  ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI
1461 
 
1462 
      -- CPX $xxxx (absolute)
1463 
      when  ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1464 
      when  ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1465 
      when  ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI
1466 
 
1467 
      -- CPY $xxxx (absolute)
1468 
      when  ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1469 
      when  ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1470 
      when  ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI
1471 
 
1472 
      -- ORA $xxxx (absolute)
1473 
      when  ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1474 
      when  ABORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1475 
      when  ABORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A=A OR MEM; EI
1476 
 
1477 
      -- AND $xxxx (absolute)
1478 
      when  ABAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1479 
      when  ABAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1480 
      when  ABAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A=A AND MEM; EI
1481 
 
1482 
      -- EOR $xxxx (absolute)
1483 
      when  ABEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1484 
      when  ABEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1485 
      when  ABEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A=A XOR MEM; EI
1486 
 
1487 
      -- ASL $xxxx (absolute)
1488 
      when  ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1489 
      when  ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1490 
      when  ABASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1491 
      when  ABASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1492 
      when  ABASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1493 
 
1494 
      -- LSR $xxxx (absolute)
1495 
      when  ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1496 
      when  ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1497 
      when  ABLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1498 
      when  ABLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1499 
      when  ABLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1500 
 
1501 
      -- ROL $xxxx (absolute)
1502 
      when  ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1503 
      when  ABROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1504 
      when  ABROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1505 
      when  ABROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1506 
      when  ABROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1507 
 
1508 
      -- ROR $xxxx (absolute)
1509 
      when  ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1510 
      when  ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1511 
      when  ABROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1512 
      when  ABROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1513 
      when  ABROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1514 
 
1515 
      -- INC $xxxx (absolute)
1516 
      when  ABINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1517 
      when  ABINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1518 
      when  ABINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1519 
      when  ABINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1520 
      when  ABINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1521 
 
1522 
      -- DEC $xxxx (absolute)
1523 
      when  ABDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1524 
      when  ABDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1525 
      when  ABDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1526 
      when  ABDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1527 
      when  ABDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1528 
 
1529 
      -- TSB $xxxx (absolute)
1530 
      when  ABTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1531 
      when  ABTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1532 
      when  ABTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1533 
      when  ABTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1534 
      when  ABTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O
1535 
      when  ABTSB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1536 
 
1537 
      -- TRB $xxxx (absolute)
1538 
      when  ABTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1539 
      when  ABTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1540 
      when  ABTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1541 
      when  ABTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1542 
      when  ABTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O => O
1543 
      when  ABTRB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1544 
 
1545 
      ------------------------------------
1546 
      --          ABSOLUTE,X            --
1547 
      ------------------------------------
1548 
      --                      DMUX: ALU operand #2 multiplexer
1549 
      --                      |       AI: effective address is indexed (X or Y)
1550 
      --                      |       |   VP: vector pull
1551 
      --                      |       |   |   BR: branch opcode
1552 
      --                      |       |   |   |   EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
1553 
      --                      |       |   |   |   |   W: read/write control
1554 
      --                      |       |   |   |   |   |    CLI: clear interrupt request
1555 
      --                      |       |   |   |   |   |    |    PD: PC/MP address output multiplexer select
1556 
      --                      |       |   |   |   |   |    |    |      PCR: register PC (program counter)
1557 
      --                      |       |   |   |   |   |    |    |      |        MPR: register MP (memory pointer)
1558 
      --                      |       |   |   |   |   |    |    |      |        |       P_OP: register P set/reset bit
1559 
      --                      |       |   |   |   |   |    |    |      |        |       |       ALUOP: ALU operation
1560 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       REGOP: registers load/increment/decrement etc.
1561 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       RSEL: registers output multiplexer select
1562 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       |
1563 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       |
1564 
      --                   -- DMUX    AI  VP  BR  EI  W    CLI  PD     PCR      MPR     P_OP    ALUOP   REGOP   RSEL
1565 
      -- LDA $xxxx,X (absolute indexed)
1566 
      when  AXLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1567 
      when  AXLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1568 
      when  AXLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1569 
      when  AXLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1570 
 
1571 
      -- LDY $xxxx,X (absolute indexed)
1572 
      when  AXLDY_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1573 
      when  AXLDY_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1574 
      when  AXLDY_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y, MP_MSB+CARRY, EI
1575 
      when  AXLDY_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
1576 
 
1577 
      -- STA $xxxx,X (absolute indexed)
1578 
      when  AXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1579 
      when  AXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1580 
      when  AXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1581 
      when  AXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1582 
 
1583 
      -- STZ $xxxx,X (absolute indexed)
1584 
      when  AXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1585 
      when  AXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1586 
      when  AXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1587 
      when  AXSTZ_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI
1588 
 
1589 
      -- ADC $xxxx,X (absolute indexed)
1590 
      when  AXADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1591 
      when  AXADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1592 
      when  AXADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
1593 
      when  AXADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1594 
      when  AXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1595 
 
1596 
      -- SBC $xxxx,X (absolute indexed)
1597 
      when  AXSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1598 
      when  AXSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1599 
      when  AXSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
1600 
      when  AXSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1601 
      when  AXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1602 
 
1603 
      -- CMP $xxxx,X (absolute indexed)
1604 
      when  AXCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1605 
      when  AXCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1606 
      when  AXCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1607 
      when  AXCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
1608 
 
1609 
      -- INC $xxxx,X (absolute indexed)
1610 
      when  AXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1611 
      when  AXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1612 
      when  AXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1613 
      when  AXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1614 
      when  AXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1615 
      when  AXINC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1616 
 
1617 
      -- DEC $xxxx,X (absolute indexed)
1618 
      when  AXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1619 
      when  AXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1620 
      when  AXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1621 
      when  AXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1622 
      when  AXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1623 
      when  AXDEC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1624 
 
1625 
      -- ASL $xxxx,X (absolute indexed)
1626 
      when  AXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1627 
      when  AXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1628 
      when  AXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1629 
      when  AXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1630 
      when  AXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT
1631 
      when  AXASL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1632 
 
1633 
      -- LSR $xxxx,X (absolute indexed)
1634 
      when  AXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1635 
      when  AXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1636 
      when  AXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1637 
      when  AXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1638 
      when  AXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT
1639 
      when  AXLSR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1640 
 
1641 
      -- ROL $xxxx,X (absolute indexed)
1642 
      when  AXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1643 
      when  AXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1644 
      when  AXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1645 
      when  AXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1646 
      when  AXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT
1647 
      when  AXROL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1648 
 
1649 
      -- ROR $xxxx,X (absolute indexed)
1650 
      when  AXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1651 
      when  AXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1652 
      when  AXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1653 
      when  AXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1654 
      when  AXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT
1655 
      when  AXROR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1656 
 
1657 
      -- AND $xxxx,X (absolute indexed)
1658 
      when  AXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1659 
      when  AXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1660 
      when  AXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1661 
      when  AXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
1662 
 
1663 
      -- ORA $xxxx,X (absolute indexed)
1664 
      when  AXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1665 
      when  AXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1666 
      when  AXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1667 
      when  AXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
1668 
 
1669 
      -- EOR $xxxx,X (absolute indexed)
1670 
      when  AXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1671 
      when  AXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1672 
      when  AXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1673 
      when  AXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
1674 
 
1675 
      -- BIT $xxxx,X (absolute indexed)
1676 
      when  AXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1677 
      when  AXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1678 
      when  AXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1679 
      when  AXBIT_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; EXT BIT A; EI
1680 
 
1681 
      ------------------------------------
1682 
      --          ABSOLUTE,Y            --
1683 
      ------------------------------------
1684 
      -- LDA $xxxx,X (absolute indexed)
1685 
      when  AYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1686 
      when  AYLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1687 
      when  AYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1688 
      when  AYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1689 
 
1690 
      -- LDX $xxxx,Y (absolute indexed)
1691 
      when  AYLDX_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1692 
      when  AYLDX_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1693 
      when  AYLDX_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; MP_MSB+CARRY, EI
1694 
      when  AYLDX_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
1695 
 
1696 
      -- STA $xxxx,Y (absolute indexed)
1697 
      when  AYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1698 
      when  AYSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1699 
      when  AYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1700 
      when  AYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1701 
 
1702 
      -- ADC $xxxx,Y (absolute indexed)
1703 
      when  AYADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1704 
      when  AYADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1705 
      when  AYADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
1706 
      when  AYADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1707 
      when  AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1708 
 
1709 
      -- SBC $xxxx,Y (absolute indexed)
1710 
      when  AYSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1711 
      when  AYSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1712 
      when  AYSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
1713 
      when  AYSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1714 
      when  AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1715 
 
1716 
      -- CMP $xxxx,Y (absolute indexed)
1717 
      when  AYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1718 
      when  AYCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1719 
      when  AYCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1720 
      when  AYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
1721 
 
1722 
      -- AND $xxxx,Y (absolute indexed)
1723 
      when  AYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1724 
      when  AYAND_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1725 
      when  AYAND_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; MP_MSB+CARRY, EI
1726 
      when  AYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
1727 
 
1728 
      -- ORA $xxxx,Y (absolute indexed)
1729 
      when  AYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1730 
      when  AYORA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1731 
      when  AYORA_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; MP_MSB+CARRY, EI
1732 
      when  AYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
1733 
 
1734 
      -- EOR $xxxx,Y (absolute indexed)
1735 
      when  AYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1736 
      when  AYEOR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1737 
      when  AYEOR_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; MP_MSB+CARRY, EI
1738 
      when  AYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
1739 
 
1740 
      ------------------------------------
1741 
      --            RELATIVE            --
1742 
      ------------------------------------
1743 
      -- BRA xx
1744 
      when    BRA_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1745 
      when    BRA_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1746 
      when    BRA_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1747 
 
1748 
      -- BEQ xx
1749 
      when    BEQ_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1750 
      when    BEQ_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1751 
      when    BEQ_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1752 
 
1753 
      -- BNE xx
1754 
      when    BNE_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1755 
      when    BNE_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1756 
      when    BNE_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1757 
 
1758 
      -- BCC xx
1759 
      when    BCC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1760 
      when    BCC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1761 
      when    BCC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1762 
 
1763 
      -- BCS xx
1764 
      when    BCS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1765 
      when    BCS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1766 
      when    BCS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1767 
 
1768 
      -- BVC xx
1769 
      when    BVC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1770 
      when    BVC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1771 
      when    BVC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1772 
 
1773 
      -- BVS xx
1774 
      when    BVS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1775 
      when    BVS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1776 
      when    BVS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1777 
 
1778 
      -- BPL xx
1779 
      when    BPL_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1780 
      when    BPL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1781 
      when    BPL_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1782 
 
1783 
      -- BMI xx
1784 
      when    BMI_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1785 
      when    BMI_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1786 
      when    BMI_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1787 
 
1788 
      when    others  => q <= NOP_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
1789 
    end case;
1790 
  end process;
1791 
end comb;
1792 
 
1793 
 

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