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[/] [v6502/] [trunk/] [mcpla.vhd] - Blame information for rev 6

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1 4 Valerio63 
library IEEE;
2 
use IEEE.std_logic_1164.all;  -- defines std_logic types
3 
use IEEE.STD_LOGIC_unsigned.all;
4 
use IEEE.STD_LOGIC_arith.all;
5 
 
6 
-- microcode PLA (NMOS 6502 opcode mask covering)
7 
-- Written by Valerio Venturi
8 
-- output fields format:
9 
-- fields:
10 
-- RSEL:  registers output multiplexer select
11 
-- REGOP: registers load/increment/decrement etc.
12 
-- ALUOP: ALU operation
13 
-- P_OP:  register P set/reset bit
14 
-- MPR:   register MP
15 
-- PCR:   register PC
16 
-- CLI:   clear interrupt request
17 
-- BR:    branch opcode
18 
-- EI:    end of microcode sequence
19 
-- W:     read/write control
20 
-- PD:    PC/MP output multiplexer select
21 
entity mcpla is
22 
  port(    a:  in STD_LOGIC_VECTOR(10 downto 0);
23 
           q: out STD_LOGIC_VECTOR(34 downto 0)
24 
      );
25 
end mcpla;
26 
 
27 
architecture comb of mcpla is
28 
 
29 
------------------------------------
30 
--            IMPLIED             --
31 
------------------------------------
32 
constant   NOP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101010000"; -- 0xEA NOP
33 
 
34 
-- interrupts
35 
constant   BRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000000000"; -- 0x00 BRK/IRQ/NMI/RES
36 
constant   BRK_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000000001"; -- 0x00 BRK/IRQ/NMI/RES
37 
constant   BRK_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000000010"; -- 0x00 BRK/IRQ/NMI/RES
38 
constant   BRK_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000000011"; -- 0x00 BRK/IRQ/NMI/RES
39 
constant   BRK_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000000100"; -- 0x00 BRK/IRQ/NMI/RES
40 
constant   BRK_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00000000101"; -- 0x00 BRK/IRQ/NMI/RES
41 
constant   BRK_OP6: STD_LOGIC_VECTOR(10 downto 0) := "00000000110"; -- 0x00 BRK/IRQ/NMI/RES
42 
 
43 
-- IMPLIED
44 
constant   CLC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011000000"; -- 0x18 CLC 0->C
45 
constant   SEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111000000"; -- 0x38 SEC 1->C
46 
constant   CLI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011000000"; -- 0x58 CLI 0->I
47 
constant   SEI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111000000"; -- 0x78 SEI 1->I
48 
constant   CLV_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111000000"; -- 0xB8 CLV 0->V
49 
constant   CLD_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011000000"; -- 0xD8 CLD 0->D
50 
constant   SED_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111000000"; -- 0xF8 SED 1->D
51 
constant   TAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101010000"; -- 0xAA TAX A->X
52 
constant   TAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101000000"; -- 0xA8 TAY A->Y
53 
constant   TXA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001010000"; -- 0x8A TXA X->A
54 
constant   TYA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011000000"; -- 0x98 TYA Y->A
55 
constant   TXY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011011000"; -- 0x9B TXY X->Y
56 
constant   TYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111011000"; -- 0xBB TYX Y->X
57 
constant   TXS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011010000"; -- 0x9A TXS X->S
58 
constant   TSX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111010000"; -- 0xBA TSX S->X
59 
constant   TAZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011011000"; -- 0x1B TAZ A->Z
60 
constant   TZA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111011000"; -- 0x3B TZA Z->A
61 
constant   PHP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001000000"; -- 0x08 PHP P->S
62 
constant   PHA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001000000"; -- 0x48 PHA A->S
63 
constant   PHX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011010000"; -- 0xDA PHX X->S
64 
constant   PHY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011010000"; -- 0x5A PHY X->S
65 
constant   PHR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001011000"; -- 0x8B PHR AXY->S
66 
constant   PHR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001011001"; -- 0x8B PHR AXY->S
67 
constant   PHR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001011010"; -- 0x8B PHR AXY->S
68 
constant   PLP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101000000"; -- 0x28 PLP S->P
69 
constant   PLP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101000001"; -- 0x28 PLP S->P
70 
constant   PLA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101000000"; -- 0x68 PLA S->A
71 
constant   PLA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101000001"; -- 0x68 PLA S->A
72 
constant   PLX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111010000"; -- 0xFA PLX S->X
73 
constant   PLX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111010001"; -- 0xFA PLX S->X
74 
constant   PLY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111010000"; -- 0x7A PLY S->Y
75 
constant   PLY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111010001"; -- 0x7A PLY S->Y
76 
constant   PLR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101011000"; -- 0xAB PLR S->YXA
77 
constant   PLR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101011001"; -- 0xAB PLR S->YXA
78 
constant   PLR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101011010"; -- 0xAB PLR S->YXA
79 
constant   PLR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10101011011"; -- 0xAB PLR S->YXA
80 
constant   INC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011010000"; -- 0x1A INC A +1
81 
constant   DEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111010000"; -- 0x3A DEC A -1
82 
constant   INX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101000000"; -- 0xE8 INX X +1
83 
constant   DEX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001010000"; -- 0xCA DEX X -1
84 
constant   INY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001000000"; -- 0xC8 INY Y +1
85 
constant   DEY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001000000"; -- 0x88 DEY Y -1
86 
constant   RTS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100000000"; -- 0x60 RTS
87 
constant   RTS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100000001"; -- 0x60 RTS
88 
constant   RTS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100000010"; -- 0x60 RTS
89 
constant   RTS_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100000011"; -- 0x60 RTS
90 
constant   RTS_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100000100"; -- 0x60 RTS
91 
constant   RTI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000000000"; -- 0x40 RTI
92 
constant   RTI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000000001"; -- 0x40 RTI
93 
constant   RTI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000000010"; -- 0x40 RTI
94 
constant   RTI_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000000011"; -- 0x40 RTI
95 
constant   RTI_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01000000100"; -- 0x40 RTI
96 
constant   RTI_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01000000101"; -- 0x40 RTI
97 
constant   ASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001010000"; -- 0x0A ASL A
98 
constant   LSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001010000"; -- 0x4A LSR A
99 
constant   ROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101010000"; -- 0x2A ROL A
100 
constant   ROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101010000"; -- 0x6A ROR A
101 
constant   XYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101011000"; -- 0xEB EXCHANGE X <-> Y
102 
constant   XYX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101011001"; -- 0xEB EXCHANGE X <-> Y
103 
constant   XYX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101011010"; -- 0xEB EXCHANGE X <-> Y
104 
constant   XAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001011000"; -- 0x0B EXCHANGE A <-> X
105 
constant   XAX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001011001"; -- 0x0B EXCHANGE A <-> X
106 
constant   XAX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001011010"; -- 0x0B EXCHANGE A <-> X
107 
constant   XAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101011000"; -- 0x2B EXCHANGE A <-> Y
108 
constant   XAY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101011001"; -- 0x2B EXCHANGE A <-> Y
109 
constant   XAY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101011010"; -- 0x2B EXCHANGE A <-> Y
110 
constant   ISP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001011000"; -- 0x4B init SP X -> S lsb; A -> S msb
111 
constant   ISP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001011001"; -- 0x4B init SP X -> S lsb; A -> S msb
112 
constant   TSP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011011000"; -- 0x5B transfer SP S lsb -> X; S msb -> A
113 
constant   TSP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011011001"; -- 0x5B transfer SP S lsb -> X; S msb -> A
114 
 
115 
------------------------------------
116 
--           IMMEDIATE            --
117 
------------------------------------
118 
constant IMLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101001000"; -- 0xA9 LDA #IMM
119 
constant IMLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100010000"; -- 0xA2 LDX #IMM
120 
constant IMLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100000000"; -- 0xA0 LDY #IMM
121 
constant IMADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101001000"; -- 0x69 ADC #IMM
122 
constant IMADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101001001"; -- 0x69 ADC #IMM
123 
constant IMSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101001000"; -- 0xE9 SBC #IMM
124 
constant IMSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101001001"; -- 0xE9 SBC #IMM
125 
constant IMAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101001000"; -- 0x29 AND #IMM
126 
constant IMORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001001000"; -- 0x09 ORA #IMM
127 
constant IMEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001001000"; -- 0x49 EOR #IMM
128 
constant IMCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001001000"; -- 0xC9 CMP #IMM
129 
constant IMCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100000000"; -- 0xE0 CPX #IMM
130 
constant IMCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000000000"; -- 0xC0 CPY #IMM
131 
constant IMBRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001001000"; -- 0x89 BRK #IMM
132 
 
133 
------------------------------------
134 
--           ZERO PAGE            --
135 
------------------------------------
136 
constant ZPLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100101000"; -- 0xA5 LDA ZP
137 
constant ZPLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100101001"; -- 0xA5 LDA ZP
138 
constant ZPLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100110000"; -- 0xA6 LDX ZP
139 
constant ZPLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100110001"; -- 0xA6 LDX ZP
140 
constant ZPLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100100000"; -- 0xA4 LDY ZP
141 
constant ZPLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100100001"; -- 0xA4 LDY ZP
142 
constant ZPSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000101000"; -- 0x85 STA ZP
143 
constant ZPSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000101001"; -- 0x85 STA ZP
144 
constant ZPSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000110000"; -- 0x86 STX ZP
145 
constant ZPSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000110001"; -- 0x86 STX ZP
146 
constant ZPSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000100000"; -- 0x84 STY ZP
147 
constant ZPSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000100001"; -- 0x84 STY ZP
148 
constant ZPSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100100000"; -- 0x64 STZ ZP
149 
constant ZPSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100100001"; -- 0x64 STZ ZP
150 
constant ZPADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100101000"; -- 0x65 ADC ZP
151 
constant ZPADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100101001"; -- 0x65 ADC ZP
152 
constant ZPADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100101010"; -- 0x65 ADC ZP
153 
constant ZPSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100101000"; -- 0xE5 SBC ZP
154 
constant ZPSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100101001"; -- 0xE5 SBC ZP
155 
constant ZPSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100101010"; -- 0xE5 SBC ZP
156 
constant ZPCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000101000"; -- 0xC5 CMP ZP
157 
constant ZPCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000101001"; -- 0xC5 CMP ZP
158 
constant ZPCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100100000"; -- 0xE4 CPX ZP
159 
constant ZPCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100100001"; -- 0xE4 CPX ZP
160 
constant ZPCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000100000"; -- 0xC4 CPY ZP
161 
constant ZPCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000100001"; -- 0xC4 CPY ZP
162 
constant ZPAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100101000"; -- 0x25 AND ZP
163 
constant ZPAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100101001"; -- 0x25 AND ZP
164 
constant ZPORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000101000"; -- 0x05 ORA ZP
165 
constant ZPORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000101001"; -- 0x05 ORA ZP
166 
constant ZPEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000101000"; -- 0x45 EOR ZP
167 
constant ZPEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000101001"; -- 0x45 EOR ZP
168 
constant ZPBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100100000"; -- 0x24 BIT ZP
169 
constant ZPBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100100001"; -- 0x24 BIT ZP
170 
constant ZPASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000110000"; -- 0x06 ASL ZP
171 
constant ZPASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000110001"; -- 0x06 ASL ZP
172 
constant ZPASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000110010"; -- 0x06 ASL ZP
173 
constant ZPASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000110011"; -- 0x06 ASL ZP
174 
constant ZPLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000110000"; -- 0x46 LSR ZP
175 
constant ZPLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000110001"; -- 0x46 LSR ZP
176 
constant ZPLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000110010"; -- 0x46 LSR ZP
177 
constant ZPLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000110011"; -- 0x46 LSR ZP
178 
constant ZPROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100110000"; -- 0x26 ROL ZP
179 
constant ZPROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100110001"; -- 0x26 ROL ZP
180 
constant ZPROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100110010"; -- 0x26 ROL ZP
181 
constant ZPROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100110011"; -- 0x26 ROL ZP
182 
constant ZPROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100110000"; -- 0x66 ROR ZP
183 
constant ZPROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100110001"; -- 0x66 ROR ZP
184 
constant ZPROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100110010"; -- 0x66 ROR ZP
185 
constant ZPROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100110011"; -- 0x66 ROR ZP
186 
constant ZPINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100110000"; -- 0xE6 INC ZP
187 
constant ZPINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100110001"; -- 0xE6 INC ZP
188 
constant ZPINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100110010"; -- 0xE6 INC ZP
189 
constant ZPINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100110011"; -- 0xE6 INC ZP
190 
constant ZPDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000110000"; -- 0xC6 DEC ZP
191 
constant ZPDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000110001"; -- 0xC6 DEC ZP
192 
constant ZPDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000110010"; -- 0xC6 DEC ZP
193 
constant ZPDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000110011"; -- 0xC6 DEC ZP
194 
constant ZPTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000100000"; -- 0x04 TSB ZP
195 
constant ZPTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000100001"; -- 0x04 TSB ZP
196 
constant ZPTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000100010"; -- 0x04 TSB ZP
197 
constant ZPTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000100011"; -- 0x04 TSB ZP
198 
constant ZPTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000100100"; -- 0x04 TSB ZP
199 
constant ZPTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010100000"; -- 0x14 TRB ZP
200 
constant ZPTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010100001"; -- 0x14 TRB ZP
201 
constant ZPTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010100010"; -- 0x14 TRB ZP
202 
constant ZPTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010100011"; -- 0x14 TRB ZP
203 
constant ZPTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010100100"; -- 0x14 TRB ZP
204 
 
205 
------------------------------------
206 
--          ZERO PAGE,X           --
207 
------------------------------------
208 
constant ZXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110101000"; -- 0xB5 LDA ZP,X
209 
constant ZXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110101001"; -- 0xB5 LDA ZP,X
210 
constant ZXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110101010"; -- 0xB5 LDA ZP,X
211 
constant ZXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110100000"; -- 0xB4 LDY ZP,X
212 
constant ZXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110100001"; -- 0xB4 LDY ZP,X
213 
constant ZXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110100010"; -- 0xB4 LDY ZP,X
214 
constant ZXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010101000"; -- 0x95 STA ZP,X
215 
constant ZXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010101001"; -- 0x95 STA ZP,X
216 
constant ZXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010101010"; -- 0x95 STA ZP,X
217 
constant ZXSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010100000"; -- 0x94 STY ZP,X
218 
constant ZXSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010100001"; -- 0x94 STY ZP,X
219 
constant ZXSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010100010"; -- 0x94 STY ZP,X
220 
constant ZXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110100000"; -- 0x74 STZ ZP,X
221 
constant ZXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110100001"; -- 0x74 STZ ZP,X
222 
constant ZXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110100010"; -- 0x74 STZ ZP,X
223 
constant ZXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110101000"; -- 0x75 ADC ZP,X
224 
constant ZXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110101001"; -- 0x75 ADC ZP,X
225 
constant ZXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110101010"; -- 0x75 ADC ZP,X
226 
constant ZXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110101011"; -- 0x75 ADC ZP,X
227 
constant ZXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110101000"; -- 0xF5 SBC ZP,X
228 
constant ZXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110101001"; -- 0xF5 SBC ZP,X
229 
constant ZXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110101010"; -- 0xF5 SBC ZP,X
230 
constant ZXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110101011"; -- 0xF5 SBC ZP,X
231 
constant ZXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010101000"; -- 0xD5 CMP ZP,X
232 
constant ZXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010101001"; -- 0xD5 CMP ZP,X
233 
constant ZXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010101010"; -- 0xD5 CMP ZP,X
234 
constant ZXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110101000"; -- 0x35 AND ZP,X
235 
constant ZXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110101001"; -- 0x35 AND ZP,X
236 
constant ZXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110101010"; -- 0x35 AND ZP,X
237 
constant ZXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010101000"; -- 0x15 ORA ZP,X
238 
constant ZXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010101001"; -- 0x15 ORA ZP,X
239 
constant ZXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010101010"; -- 0x15 ORA ZP,X
240 
constant ZXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010101000"; -- 0x55 EOR ZP,X
241 
constant ZXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010101001"; -- 0x55 EOR ZP,X
242 
constant ZXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010101010"; -- 0x55 EOR ZP,X
243 
constant ZXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010110000"; -- 0x16 ASL ZP,X
244 
constant ZXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010110001"; -- 0x16 ASL ZP,X
245 
constant ZXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010110010"; -- 0x16 ASL ZP,X
246 
constant ZXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010110011"; -- 0x16 ASL ZP,X
247 
constant ZXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010110100"; -- 0x16 ASL ZP,X
248 
constant ZXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010110000"; -- 0x56 LSR ZP,X
249 
constant ZXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010110001"; -- 0x56 LSR ZP,X
250 
constant ZXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010110010"; -- 0x56 LSR ZP,X
251 
constant ZXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010110011"; -- 0x56 LSR ZP,X
252 
constant ZXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010110100"; -- 0x56 LSR ZP,X
253 
constant ZXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110110000"; -- 0x36 ROL ZP,X
254 
constant ZXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110110001"; -- 0x36 ROL ZP,X
255 
constant ZXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110110010"; -- 0x36 ROL ZP,X
256 
constant ZXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110110011"; -- 0x36 ROL ZP,X
257 
constant ZXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110110100"; -- 0x36 ROL ZP,X
258 
constant ZXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110110000"; -- 0x76 ROR ZP,X
259 
constant ZXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110110001"; -- 0x76 ROR ZP,X
260 
constant ZXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110110010"; -- 0x76 ROR ZP,X
261 
constant ZXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110110011"; -- 0x76 ROR ZP,X
262 
constant ZXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110110100"; -- 0x76 ROR ZP,X
263 
constant ZXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010110000"; -- 0xD6 DEC ZP,X
264 
constant ZXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010110001"; -- 0xD6 DEC ZP,X
265 
constant ZXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010110010"; -- 0xD6 DEC ZP,X
266 
constant ZXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010110011"; -- 0xD6 DEC ZP,X
267 
constant ZXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010110100"; -- 0xD6 DEC ZP,X
268 
constant ZXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110110000"; -- 0xF6 INC ZP,X
269 
constant ZXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110110001"; -- 0xF6 INC ZP,X
270 
constant ZXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110110010"; -- 0xF6 INC ZP,X
271 
constant ZXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110110011"; -- 0xF6 INC ZP,X
272 
constant ZXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110110100"; -- 0xF6 INC ZP,X
273 
constant ZXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110100000"; -- 0x34 BIT ZP,X
274 
constant ZXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110100001"; -- 0x34 BIT ZP,X
275 
constant ZXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110100010"; -- 0x34 BIT ZP,X
276 
 
277 
------------------------------------
278 
--          ZERO PAGE,Y           --
279 
------------------------------------
280 
constant ZYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110110000"; -- 0xB6 LDX ZP,Y
281 
constant ZYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110110001"; -- 0xB6 LDX ZP,Y
282 
constant ZYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110110010"; -- 0xB6 LDX ZP,Y
283 
constant ZYSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010110000"; -- 0x96 STX ZP,Y
284 
constant ZYSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010110001"; -- 0x96 STX ZP,Y
285 
constant ZYSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010110010"; -- 0x96 STX ZP,Y
286 
 
287 
------------------------------------
288 
--           INDIRECT             --
289 
------------------------------------
290 
constant INJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101100000"; -- 0x6C JMP (IND)
291 
constant INJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101100001"; -- 0x6C JMP (IND)
292 
constant INJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101100010"; -- 0x6C JMP (IND)
293 
constant INJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101100011"; -- 0x6C JMP (IND)
294 
 
295 
------------------------------------
296 
--          INDIRECT,Y            --
297 
------------------------------------
298 
constant IYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110001000"; -- 0xB1 LDA (IND_ZP),Y
299 
constant IYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110001001"; -- 0xB1 LDA (IND_ZP),Y
300 
constant IYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110001010"; -- 0xB1 LDA (IND_ZP),Y
301 
constant IYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10110001011"; -- 0xB1 LDA (IND_ZP),Y
302 
constant IYLDA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10110001100"; -- 0xB1 LDA (IND_ZP),Y
303 
constant IYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010001000"; -- 0x91 STA (IND_ZP),Y
304 
constant IYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010001001"; -- 0x91 STA (IND_ZP),Y
305 
constant IYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010001010"; -- 0x91 STA (IND_ZP),Y
306 
constant IYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10010001011"; -- 0x91 STA (IND_ZP),Y
307 
constant IYSTA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10010001100"; -- 0x91 STA (IND_ZP),Y
308 
constant IYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110001000"; -- 0x71 ADC (IND_ZP),Y
309 
constant IYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110001001"; -- 0x71 ADC (IND_ZP),Y
310 
constant IYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110001010"; -- 0x71 ADC (IND_ZP),Y
311 
constant IYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110001011"; -- 0x71 ADC (IND_ZP),Y
312 
constant IYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110001100"; -- 0x71 ADC (IND_ZP),Y
313 
constant IYADC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01110001101"; -- 0x71 ADC (IND_ZP),Y
314 
constant IYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110001000"; -- 0xF1 SBC (IND_ZP),Y
315 
constant IYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110001001"; -- 0xF1 SBC (IND_ZP),Y
316 
constant IYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110001010"; -- 0xF1 SBC (IND_ZP),Y
317 
constant IYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110001011"; -- 0xF1 SBC (IND_ZP),Y
318 
constant IYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110001100"; -- 0xF1 SBC (IND_ZP),Y
319 
constant IYSBC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11110001101"; -- 0xF1 SBC (IND_ZP),Y
320 
constant IYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010001000"; -- 0xD1 CMP (IND_ZP),Y
321 
constant IYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010001001"; -- 0xD1 CMP (IND_ZP),Y
322 
constant IYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010001010"; -- 0xD1 CMP (IND_ZP),Y
323 
constant IYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010001011"; -- 0xD1 CMP (IND_ZP),Y
324 
constant IYCMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010001100"; -- 0xD1 CMP (IND_ZP),Y
325 
constant IYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110001000"; -- 0x31 AND (IND_ZP),Y
326 
constant IYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110001001"; -- 0x31 AND (IND_ZP),Y
327 
constant IYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110001010"; -- 0x31 AND (IND_ZP),Y
328 
constant IYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110001011"; -- 0x31 AND (IND_ZP),Y
329 
constant IYAND_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110001100"; -- 0x31 AND (IND_ZP),Y
330 
constant IYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010001000"; -- 0x11 ORA (IND_ZP),Y
331 
constant IYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010001001"; -- 0x11 ORA (IND_ZP),Y
332 
constant IYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010001010"; -- 0x11 ORA (IND_ZP),Y
333 
constant IYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010001011"; -- 0x11 ORA (IND_ZP),Y
334 
constant IYORA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010001100"; -- 0x11 ORA (IND_ZP),Y
335 
constant IYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010001000"; -- 0x51 EOR (IND_ZP),Y
336 
constant IYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010001001"; -- 0x51 EOR (IND_ZP),Y
337 
constant IYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010001010"; -- 0x51 EOR (IND_ZP),Y
338 
constant IYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010001011"; -- 0x51 EOR (IND_ZP),Y
339 
constant IYEOR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010001100"; -- 0x51 EOR (IND_ZP),Y
340 
 
341 
------------------------------------
342 
--          INDIRECT,X            --
343 
------------------------------------
344 
constant IXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100001000"; -- 0xA1 LDA (IND_ZP,X)
345 
constant IXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100001001"; -- 0xA1 LDA (IND_ZP,X)
346 
constant IXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10100001010"; -- 0xA1 LDA (IND_ZP,X)
347 
constant IXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10100001011"; -- 0xA1 LDA (IND_ZP,X)
348 
constant IXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000001000"; -- 0x81 STA (IND_ZP,X)
349 
constant IXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000001001"; -- 0x81 STA (IND_ZP,X)
350 
constant IXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000001010"; -- 0x81 STA (IND_ZP,X)
351 
constant IXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10000001011"; -- 0x81 STA (IND_ZP,X)
352 
constant IXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100001000"; -- 0x21 AND (IND_ZP,X)
353 
constant IXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100001001"; -- 0x21 AND (IND_ZP,X)
354 
constant IXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100001010"; -- 0x21 AND (IND_ZP,X)
355 
constant IXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100001011"; -- 0x21 AND (IND_ZP,X)
356 
constant IXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000001000"; -- 0x01 ORA (IND_ZP,X)
357 
constant IXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000001001"; -- 0x01 ORA (IND_ZP,X)
358 
constant IXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000001010"; -- 0x01 ORA (IND_ZP,X)
359 
constant IXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000001011"; -- 0x01 ORA (IND_ZP,X)
360 
constant IXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000001000"; -- 0x41 EOR (IND_ZP,X)
361 
constant IXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000001001"; -- 0x41 EOR (IND_ZP,X)
362 
constant IXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000001010"; -- 0x41 EOR (IND_ZP,X)
363 
constant IXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000001011"; -- 0x41 EOR (IND_ZP,X)
364 
constant IXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000001000"; -- 0xC1 CMP (IND_ZP,X)
365 
constant IXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000001001"; -- 0xC1 CMP (IND_ZP,X)
366 
constant IXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000001010"; -- 0xC1 CMP (IND_ZP,X)
367 
constant IXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000001011"; -- 0xC1 CMP (IND_ZP,X)
368 
constant IXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100001000"; -- 0x61 ADC (IND_ZP,X)
369 
constant IXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100001001"; -- 0x61 ADC (IND_ZP,X)
370 
constant IXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100001010"; -- 0x61 ADC (IND_ZP,X)
371 
constant IXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100001011"; -- 0x61 ADC (IND_ZP,X)
372 
constant IXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100001100"; -- 0x61 ADC (IND_ZP,X)
373 
constant IXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100001000"; -- 0xE1 SBC (IND_ZP,X)
374 
constant IXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100001001"; -- 0xE1 SBC (IND_ZP,X)
375 
constant IXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100001010"; -- 0xE1 SBC (IND_ZP,X)
376 
constant IXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100001011"; -- 0xE1 SBC (IND_ZP,X)
377 
constant IXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11100001100"; -- 0xE1 SBC (IND_ZP,X)
378 
constant IXJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111100000"; -- 0x7C JMP (IND,X)
379 
constant IXJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111100001"; -- 0x7C JMP (IND,X)
380 
constant IXJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111100010"; -- 0x7C JMP (IND,X)
381 
constant IXJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111100011"; -- 0x7C JMP (IND,X)
382 
constant IXJMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111100100"; -- 0x7C JMP (IND,X)
383 
constant IXJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111100000"; -- 0xFC JSR (IND,X)
384 
constant IXJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111100001"; -- 0xFC JSR (IND,X)
385 
constant IXJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111100010"; -- 0xFC JSR (IND,X)
386 
constant IXJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111100011"; -- 0xFC JSR (IND,X)
387 
constant IXJSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111100100"; -- 0xFC JSR (IND,X)
388 
constant IXJSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111100101"; -- 0xFC JSR (IND,X)
389 
 
390 
------------------------------------
391 
--            ABSOLUTE            --
392 
------------------------------------
393 
constant ABLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101101000"; -- 0xAD LDA ABS
394 
constant ABLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101101001"; -- 0xAD LDA ABS
395 
constant ABLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101101010"; -- 0xAD LDA ABS
396 
constant ABLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101110000"; -- 0xAE LDX ABS
397 
constant ABLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101110001"; -- 0xAE LDX ABS
398 
constant ABLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101110010"; -- 0xAE LDX ABS
399 
constant ABLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101100000"; -- 0xAC LDY ABS
400 
constant ABLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101100001"; -- 0xAC LDY ABS
401 
constant ABLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101100010"; -- 0xAC LDY ABS
402 
constant ABSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001101000"; -- 0x8D STA ABS
403 
constant ABSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001101001"; -- 0x8D STA ABS
404 
constant ABSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001101010"; -- 0x8D STA ABS
405 
constant ABSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001110000"; -- 0x8E STX ABS
406 
constant ABSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001110001"; -- 0x8E STX ABS
407 
constant ABSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001110010"; -- 0x8E STX ABS
408 
constant ABSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001100000"; -- 0x8C STY ABS
409 
constant ABSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001100001"; -- 0x8C STY ABS
410 
constant ABSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001100010"; -- 0x8C STY ABS
411 
constant ABSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011100000"; -- 0x9C STZ ABS
412 
constant ABSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011100001"; -- 0x9C STZ ABS
413 
constant ABSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011100010"; -- 0x9C STZ ABS
414 
constant ABADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101101000"; -- 0x6D ADC ABS
415 
constant ABADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101101001"; -- 0x6D ADC ABS
416 
constant ABADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101101010"; -- 0x6D ADC ABS
417 
constant ABADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101101011"; -- 0x6D ADC ABS
418 
constant ABSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101101000"; -- 0xED SBC ABS
419 
constant ABSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101101001"; -- 0xED SBC ABS
420 
constant ABSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101101010"; -- 0xED SBC ABS
421 
constant ABSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101101011"; -- 0xED SBC ABS
422 
constant ABORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001101000"; -- 0x0D ORA ABS
423 
constant ABORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001101001"; -- 0x0D ORA ABS
424 
constant ABORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001101010"; -- 0x0D ORA ABS
425 
constant ABAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101101000"; -- 0x2D AND ABS
426 
constant ABAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101101001"; -- 0x2D AND ABS
427 
constant ABAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101101010"; -- 0x2D AND ABS
428 
constant ABEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001101000"; -- 0x4D EOR ABS
429 
constant ABEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001101001"; -- 0x4D EOR ABS
430 
constant ABEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001101010"; -- 0x4D EOR ABS
431 
constant ABCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001101000"; -- 0xCD CMP ABS
432 
constant ABCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001101001"; -- 0xCD CMP ABS
433 
constant ABCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001101010"; -- 0xCD CMP ABS
434 
constant ABCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101100000"; -- 0xEC CPX ABS
435 
constant ABCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101100001"; -- 0xEC CPX ABS
436 
constant ABCPX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101100010"; -- 0xEC CPX ABS
437 
constant ABCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001100000"; -- 0xCC CPY ABS
438 
constant ABCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001100001"; -- 0xCC CPY ABS
439 
constant ABCPY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001100010"; -- 0xCC CPY ABS
440 
constant ABJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001100000"; -- 0x4C JMP ABS
441 
constant ABJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001100001"; -- 0x4C JMP ABS
442 
constant ABJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100000000"; -- 0x20 JSR ABS
443 
constant ABJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100000001"; -- 0x20 JSR ABS
444 
constant ABJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100000010"; -- 0x20 JSR ABS
445 
constant ABJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100000011"; -- 0x20 JSR ABS
446 
constant ABBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101100000"; -- 0x2C BIT ABS
447 
constant ABBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101100001"; -- 0x2C BIT ABS
448 
constant ABBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101100010"; -- 0x2C BIT ABS
449 
constant ABASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001110000"; -- 0x0E ASL ABS
450 
constant ABASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001110001"; -- 0x0E ASL ABS
451 
constant ABASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001110010"; -- 0x0E ASL ABS
452 
constant ABASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001110011"; -- 0x0E ASL ABS
453 
constant ABASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001110100"; -- 0x0E ASL ABS
454 
constant ABLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001110000"; -- 0x4E LSR ABS
455 
constant ABLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001110001"; -- 0x4E LSR ABS
456 
constant ABLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001110010"; -- 0x4E LSR ABS
457 
constant ABLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01001110011"; -- 0x4E LSR ABS
458 
constant ABLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01001110100"; -- 0x4E LSR ABS
459 
constant ABROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101110000"; -- 0x2E ROL ABS
460 
constant ABROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101110001"; -- 0x2E ROL ABS
461 
constant ABROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101110010"; -- 0x2E ROL ABS
462 
constant ABROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00101110011"; -- 0x2E ROL ABS
463 
constant ABROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00101110100"; -- 0x2E ROL ABS
464 
constant ABROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101110000"; -- 0x6E ROR ABS
465 
constant ABROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101110001"; -- 0x6E ROR ABS
466 
constant ABROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101110010"; -- 0x6E ROR ABS
467 
constant ABROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101110011"; -- 0x6E ROR ABS
468 
constant ABROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01101110100"; -- 0x6E ROR ABS
469 
constant ABINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101110000"; -- 0xEE INC ABS
470 
constant ABINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101110001"; -- 0xEE INC ABS
471 
constant ABINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101110010"; -- 0xEE INC ABS
472 
constant ABINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101110011"; -- 0xEE INC ABS
473 
constant ABINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11101110100"; -- 0xEE INC ABS
474 
constant ABDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001110000"; -- 0xCE DEC ABS
475 
constant ABDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001110001"; -- 0xCE DEC ABS
476 
constant ABDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001110010"; -- 0xCE DEC ABS
477 
constant ABDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11001110011"; -- 0xCE DEC ABS
478 
constant ABDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11001110100"; -- 0xCE DEC ABS
479 
constant ABTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001100000"; -- 0x0C TSB ABS
480 
constant ABTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001100001"; -- 0x0C TSB ABS
481 
constant ABTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001100010"; -- 0x0C TSB ABS
482 
constant ABTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001100011"; -- 0x0C TSB ABS
483 
constant ABTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001100100"; -- 0x0C TSB ABS
484 
constant ABTSB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00001100101"; -- 0x0C TSB ABS
485 
constant ABTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011100000"; -- 0x1C TRB ABS
486 
constant ABTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011100001"; -- 0x1C TRB ABS
487 
constant ABTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011100010"; -- 0x1C TRB ABS
488 
constant ABTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011100011"; -- 0x1C TRB ABS
489 
constant ABTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011100100"; -- 0x1C TRB ABS
490 
constant ABTRB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011100101"; -- 0x1C TRB ABS
491 
 
492 
------------------------------------
493 
--           ABSOLUTE,X           --
494 
------------------------------------
495 
constant AXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111101000"; -- 0xBD LDA ABS,X
496 
constant AXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111101001"; -- 0xBD LDA ABS,X
497 
constant AXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111101010"; -- 0xBD LDA ABS,X
498 
constant AXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111101011"; -- 0xBD LDA ABS,X
499 
constant AXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111100000"; -- 0xBC LDY ABS,X
500 
constant AXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111100001"; -- 0xBC LDY ABS,X
501 
constant AXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111100010"; -- 0xBC LDY ABS,X
502 
constant AXLDY_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111100011"; -- 0xBC LDY ABS,X
503 
constant AXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011101000"; -- 0x9D STA ABS,X
504 
constant AXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011101001"; -- 0x9D STA ABS,X
505 
constant AXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011101010"; -- 0x9D STA ABS,X
506 
constant AXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011101011"; -- 0x9D STA ABS,X
507 
constant AXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011110000"; -- 0x9E STZ ABS,X
508 
constant AXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011110001"; -- 0x9E STZ ABS,X
509 
constant AXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011110010"; -- 0x9E STZ ABS,X
510 
constant AXSTZ_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011110011"; -- 0x9E STZ ABS,X
511 
constant AXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111101000"; -- 0x7D ADC ABS,X
512 
constant AXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111101001"; -- 0x7D ADC ABS,X
513 
constant AXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111101010"; -- 0x7D ADC ABS,X
514 
constant AXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111101011"; -- 0x7D ADC ABS,X
515 
constant AXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111101100"; -- 0x7D ADC ABS,X
516 
constant AXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111101000"; -- 0xFD SBC ABS,X
517 
constant AXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111101001"; -- 0xFD SBC ABS,X
518 
constant AXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111101010"; -- 0xFD SBC ABS,X
519 
constant AXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111101011"; -- 0xFD SBC ABS,X
520 
constant AXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111101100"; -- 0xFD SBC ABS,X
521 
constant AXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011101000"; -- 0xDD CMP ABS,X
522 
constant AXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011101001"; -- 0xDD CMP ABS,X
523 
constant AXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011101010"; -- 0xDD CMP ABS,X
524 
constant AXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011101011"; -- 0xDD CMP ABS,X
525 
constant AXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111110000"; -- 0xFE INC ABS,X
526 
constant AXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111110001"; -- 0xFE INC ABS,X
527 
constant AXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111110010"; -- 0xFE INC ABS,X
528 
constant AXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111110011"; -- 0xFE INC ABS,X
529 
constant AXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111110100"; -- 0xFE INC ABS,X
530 
constant AXINC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111110101"; -- 0xFE INC ABS,X
531 
constant AXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011110000"; -- 0xDE DEC ABS,X
532 
constant AXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011110001"; -- 0xDE DEC ABS,X
533 
constant AXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011110010"; -- 0xDE DEC ABS,X
534 
constant AXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011110011"; -- 0xDE DEC ABS,X
535 
constant AXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11011110100"; -- 0xDE DEC ABS,X
536 
constant AXDEC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11011110101"; -- 0xDE DEC ABS,X
537 
constant AXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011110000"; -- 0x1E ASL ABS,X
538 
constant AXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011110001"; -- 0x1E ASL ABS,X
539 
constant AXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011110010"; -- 0x1E ASL ABS,X
540 
constant AXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011110011"; -- 0x1E ASL ABS,X
541 
constant AXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011110100"; -- 0x1E ASL ABS,X
542 
constant AXASL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011110101"; -- 0x1E ASL ABS,X
543 
constant AXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011110000"; -- 0x5E LSR ABS,X
544 
constant AXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011110001"; -- 0x5E LSR ABS,X
545 
constant AXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011110010"; -- 0x5E LSR ABS,X
546 
constant AXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011110011"; -- 0x5E LSR ABS,X
547 
constant AXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01011110100"; -- 0x5E LSR ABS,X
548 
constant AXLSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01011110101"; -- 0x5E LSR ABS,X
549 
constant AXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111110000"; -- 0x3E ROL ABS,X
550 
constant AXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111110001"; -- 0x3E ROL ABS,X
551 
constant AXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111110010"; -- 0x3E ROL ABS,X
552 
constant AXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111110011"; -- 0x3E ROL ABS,X
553 
constant AXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00111110100"; -- 0x3E ROL ABS,X
554 
constant AXROL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00111110101"; -- 0x3E ROL ABS,X
555 
constant AXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111110000"; -- 0x7E ROR ABS,X
556 
constant AXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111110001"; -- 0x7E ROR ABS,X
557 
constant AXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111110010"; -- 0x7E ROR ABS,X
558 
constant AXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111110011"; -- 0x7E ROR ABS,X
559 
constant AXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111110100"; -- 0x7E ROR ABS,X
560 
constant AXROR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01111110101"; -- 0x7E ROR ABS,X
561 
constant AXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111101000"; -- 0x3D AND ABS,X
562 
constant AXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111101001"; -- 0x3D AND ABS,X
563 
constant AXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111101010"; -- 0x3D AND ABS,X
564 
constant AXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111101011"; -- 0x3D AND ABS,X
565 
constant AXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011101000"; -- 0x1D ORA ABS,X
566 
constant AXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011101001"; -- 0x1D ORA ABS,X
567 
constant AXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011101010"; -- 0x1D ORA ABS,X
568 
constant AXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011101011"; -- 0x1D ORA ABS,X
569 
constant AXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011101000"; -- 0x5D EOR ABS,X
570 
constant AXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011101001"; -- 0x5D EOR ABS,X
571 
constant AXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011101010"; -- 0x5D EOR ABS,X
572 
constant AXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011101011"; -- 0x5D EOR ABS,X
573 
constant AXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111100000"; -- 0x3C BIT ABS,X
574 
constant AXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111100001"; -- 0x3C BIT ABS,X
575 
constant AXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111100010"; -- 0x3C BIT ABS,X
576 
constant AXBIT_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111100011"; -- 0x3C BIT ABS,X
577 
 
578 
------------------------------------
579 
--           ABSOLUTE,Y           --
580 
------------------------------------
581 
constant AYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111001000"; -- 0xB9 LDA ABS,Y
582 
constant AYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111001001"; -- 0xB9 LDA ABS,Y
583 
constant AYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111001010"; -- 0xB9 LDA ABS,Y
584 
constant AYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111001011"; -- 0xB9 LDA ABS,Y
585 
constant AYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111110000"; -- 0xBE LDX ABS,Y
586 
constant AYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111110001"; -- 0xBE LDX ABS,Y
587 
constant AYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111110010"; -- 0xBE LDX ABS,Y
588 
constant AYLDX_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111110011"; -- 0xBE LDX ABS,Y
589 
constant AYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011001000"; -- 0x99 STA ABS,Y
590 
constant AYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011001001"; -- 0x99 STA ABS,Y
591 
constant AYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011001010"; -- 0x99 STA ABS,Y
592 
constant AYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011001011"; -- 0x99 STA ABS,Y
593 
constant AYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111001000"; -- 0x79 ADC ABS,Y
594 
constant AYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111001001"; -- 0x79 ADC ABS,Y
595 
constant AYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111001010"; -- 0x79 ADC ABS,Y
596 
constant AYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111001011"; -- 0x79 ADC ABS,Y
597 
constant AYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111001100"; -- 0x79 ADC ABS,Y
598 
constant AYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111001000"; -- 0xF9 SBC ABS,Y
599 
constant AYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111001001"; -- 0xF9 SBC ABS,Y
600 
constant AYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111001010"; -- 0xF9 SBC ABS,Y
601 
constant AYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111001011"; -- 0xF9 SBC ABS,Y
602 
constant AYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111001100"; -- 0xF9 SBC ABS,Y
603 
constant AYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011001000"; -- 0xD9 CMP ABS,Y
604 
constant AYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011001001"; -- 0xD9 CMP ABS,Y
605 
constant AYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011001010"; -- 0xD9 CMP ABS,Y
606 
constant AYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011001011"; -- 0xD9 CMP ABS,Y
607 
constant AYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011001000"; -- 0x19 ORA ABS,Y
608 
constant AYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011001001"; -- 0x19 ORA ABS,Y
609 
constant AYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011001010"; -- 0x19 ORA ABS,Y
610 
constant AYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011001011"; -- 0x19 ORA ABS,Y
611 
constant AYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111001000"; -- 0x39 AND ABS,Y
612 
constant AYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111001001"; -- 0x39 AND ABS,Y
613 
constant AYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111001010"; -- 0x39 AND ABS,Y
614 
constant AYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111001011"; -- 0x39 AND ABS,Y
615 
constant AYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011001000"; -- 0x59 EOR ABS,Y
616 
constant AYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011001001"; -- 0x59 EOR ABS,Y
617 
constant AYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011001010"; -- 0x59 EOR ABS,Y
618 
constant AYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011001011"; -- 0x59 EOR ABS,Y
619 
 
620 
------------------------------------
621 
--           RELATIVE             --
622 
------------------------------------
623 6 Valerio63 
constant BRA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000000000"; -- 0x80 BRA
624 
constant BRA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000000001"; -- 0x80 BRA
625 
constant BRA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000000010"; -- 0x80 BRA
626 
constant BCC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010000000"; -- 0x90 BCC
627 
constant BCC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010000001"; -- 0x90 BCC
628 
constant BCC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010000010"; -- 0x90 BCC
629 
constant BCS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110000000"; -- 0xB0 BCS
630 
constant BCS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110000001"; -- 0xB0 BCS
631 
constant BCS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110000010"; -- 0xB0 BCS
632 
constant BEQ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110000000"; -- 0xF0 BEQ
633 
constant BEQ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110000001"; -- 0xF0 BEQ
634 
constant BEQ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110000010"; -- 0xF0 BEQ
635 
constant BNE_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010000000"; -- 0xD0 BNE
636 
constant BNE_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010000001"; -- 0xD0 BNE
637 
constant BNE_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010000010"; -- 0xD0 BNE
638 
constant BPL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010000000"; -- 0x10 BPL
639 
constant BPL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010000001"; -- 0x10 BPL
640 
constant BPL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010000010"; -- 0x10 BPL
641 
constant BMI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110000000"; -- 0x30 BMI
642 
constant BMI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110000001"; -- 0x30 BMI
643 
constant BMI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110000010"; -- 0x30 BMI
644 
constant BVC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010000000"; -- 0x50 BVC
645 
constant BVC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010000001"; -- 0x50 BVC
646 
constant BVC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010000010"; -- 0x50 BVC
647 
constant BVS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110000000"; -- 0x70 BVS
648 
constant BVS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110000001"; -- 0x70 BVS
649 
constant BVS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110000010"; -- 0x70 BVS
650 4 Valerio63 
 
651 
-- ALU microcode
652 
constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- ALU no operation
653 
constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- ALU add with carry
654 
constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- ALU sub with borrow
655 
constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- ALU and
656 
constant  OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- ALU or
657 
constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- ALU xor
658 
constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- ALU increment by 1
659 
constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- ALU decrement by 1
660 
constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- ALU bit shift left
661 
constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- ALU bit shift right
662 
constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- ALU bit rotation left
663 
constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- ALU bit rotation right
664 
constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- ALU add without carry
665 
constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- ALU bit test
666 
constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- ALU add without carry (used for DAA decimal adjustement)
667 
constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- ALU sub without borrow (used for DAA decimal adjustement)
668 
constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- SBC without borrow in (used for CMP instruction)
669 
constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- test and set bit
670 
constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- test and reset bit
671 
 
672 
-- PCR microcode
673 
constant NOP_PC: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- PC no operation
674 
constant LSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- PC load lsb
675 
constant MSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- PC load msb
676 
constant INC_PC: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- PC increment by 1
677 
constant LOD_PC: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- PC load lsb\msb
678 
constant ADJ_PC: STD_LOGIC_VECTOR(2 downto 0) := "101"; -- PC msb adjustement (+/- by 1)
679 
 
680 
-- MPR microcode
681 
constant NOP_M: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
682 
constant LSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- load lsb
683 
constant MSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- load msb
684 
constant INC_M: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- increment LSB
685 
constant VEC_M: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- load vector
686 
constant ZPL_M: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- load ZEROPAGE
687 
constant ALL_M: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- load all 16 bit register
688 
constant ICC_M: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- increment MSB with carry
689 
constant INM_M: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- increment MSB/LSB
690 
 
691 
-- address multiplexer microcode
692 
constant ADPC: STD_LOGIC_VECTOR(1 downto 0) := "00";    -- select PC
693 
constant ADMP: STD_LOGIC_VECTOR(1 downto 0) := "01";    -- select MP
694 
constant ADSP: STD_LOGIC_VECTOR(1 downto 0) := "10";    -- select MP/SP
695 
constant ADNP: STD_LOGIC_VECTOR(1 downto 0) := "00";    -- no operation
696 
 
697 
-- PR microcode
698 
constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
699 
constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
700 6 Valerio63 
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NZ load
701 
constant FLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- NZC load
702 
constant FLV_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- NVZC load
703 
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => C
704 
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => C
705 
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => I
706 
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => I
707 
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- 1 => D
708 
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => D
709 
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- 0 => V
710 
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- auc => ACR
711 
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- hold ACR
712 
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- 1 => I/D
713 
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Z load
714 4 Valerio63 
 
715 
-- register operation microcode REGOP
716 
constant NOP_R: STD_LOGIC_VECTOR(3 downto 0) := "0000";  -- no operation
717 
constant ALD_R: STD_LOGIC_VECTOR(3 downto 0) := "0001";  -- register A load
718 
constant XLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0010";  -- register X load
719 
constant YLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0011";  -- register Y load
720 
constant ZLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0100";  -- register Z load
721 
constant OLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0101";  -- register O load
722 
constant SLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0110";  -- register S load lsb
723 
constant SLM_R: STD_LOGIC_VECTOR(3 downto 0) := "0111";  -- register S load msb
724 
constant SUP_R: STD_LOGIC_VECTOR(3 downto 0) := "1000";  -- register S increment by 1
725 
constant SDW_R: STD_LOGIC_VECTOR(3 downto 0) := "1001";  -- register S decrement by 1
726 
constant SAU_R: STD_LOGIC_VECTOR(3 downto 0) := "1010";  -- register A load/register S increment by 1
727 
constant SXU_R: STD_LOGIC_VECTOR(3 downto 0) := "1011";  -- register X load/register S increment by 1
728 
constant SYU_R: STD_LOGIC_VECTOR(3 downto 0) := "1100";  -- register Y load/register S increment by 1
729 
constant SZU_R: STD_LOGIC_VECTOR(3 downto 0) := "1101";  -- register Z load/register S increment by 1
730 
 
731 
-- register multiplexer microcode RSEL (ALU operand #1)
732 
constant EXT_O: STD_LOGIC_VECTOR(3 downto 0) := "0000";  -- external data bus
733 
constant ARD_O: STD_LOGIC_VECTOR(3 downto 0) := "0001";  -- register A select
734 
constant XRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0010";  -- register X select
735 
constant YRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0011";  -- register Y select
736 
constant SRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0100";  -- register S lsb select
737 
constant SRM_O: STD_LOGIC_VECTOR(3 downto 0) := "0101";  -- register S msb select
738 
constant PRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0110";  -- register P select
739 
constant PLR_O: STD_LOGIC_VECTOR(3 downto 0) := "0111";  -- register PCL select
740 
constant PHR_O: STD_LOGIC_VECTOR(3 downto 0) := "1000";  -- register PCH select
741 
constant ORD_O: STD_LOGIC_VECTOR(3 downto 0) := "1001";  -- register O select
742 
constant Z00_O: STD_LOGIC_VECTOR(3 downto 0) := "1010";  -- select (all zero output)
743 
constant ZRD_O: STD_LOGIC_VECTOR(3 downto 0) := "1011";  -- register Z select (all zero output)
744 
 
745 
-- data multiplexer microcode DMUX (ALU operand #2)
746 
constant NOP_D: STD_LOGIC_VECTOR(1 downto 0) := "00";
747 
constant ORD_D: STD_LOGIC_VECTOR(1 downto 0) := "01";
748 
constant EXT_D: STD_LOGIC_VECTOR(1 downto 0) := "10";
749 
constant BCD_D: STD_LOGIC_VECTOR(1 downto 0) := "11";
750 
 
751 
-- read/write control
752 
constant   RDE: STD_LOGIC_VECTOR(1 downto 0) := "11";    -- data bus read
753 
constant   WRE: STD_LOGIC_VECTOR(1 downto 0) := "10";    -- data bus write (combinatorial mode)
754 
constant   WRL: STD_LOGIC_VECTOR(1 downto 0) := "01";    -- data bus write (registered mode)
755 
 
756 
begin
757 
  process(a)
758 
  begin
759 
  -- The PLA is arranged like an ROM, there are an address input "a" and an data output "q". The address of PLA is 11 bit wide
760 
  -- and composed in this way:
761 
  --
762 
  -- ----  CPU OPCODE   ----  - MPC -
763 
  -- |                     |  |     |
764 
  -- |                     |  |     |
765 
  --  X--X--X--X--X--X--X--X--Y--Y--Y
766 
  -- 10-09-08-07-06-05-04-03-02-01-00
767 
  --
768 
  -- the bits (10-3) (X field) is formed by CPU instruction opcode
769 
  -- the bits (2-0) (Y field) is formed by the three bit wide microinstruction program counter (MPC)
770 
  -- The MPC field is cleared at each opcode fetch by FSM and since it's three bit wide there are
771 
  -- an maximum of eight microinstructions available per opcode
772 
  --
773 
  -- The bits 10-3 of PLA address serves to select the microcode group of a related CPU opcode
774 
  -- and they are stable for all instruction execution time, instead the remaining three bit 2-0 (MPC field) of PLA address
775 
  -- increment at each clock in order to address the next microcode instructions.
776 
  -- microcode assembly:
777 
  -- Due the particulary pipeline structure of this CPU, all microinstructions have an extra cycle hidden on fetch
778 
  -- of the next opcode instruction and normally this extra cycle is coded as "NOP" (see the last line  "when  others =>...").
779 
  -- However there are some instructions where this extra cycle is used for some functions like decimal adjustments etc of
780 
  -- ADC and SBC instructions (see DAA and DAS).
781 
  --
782 
  -- Microcode fields:
783 
  --
784 
  --                          DMUX: ALU operand #2 multiplexer
785 
  --                          |       AI: effective address is indexed (X or Y)
786 
  --                          |       |   VP: vector pull
787 
  --                          |       |   |   BR: branch opcode
788 
  --                          |       |   |   |   EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
789 
  --                          |       |   |   |   |   W: read/write control
790 
  --                          |       |   |   |   |   |    CLI: clear interrupt request
791 
  --                          |       |   |   |   |   |    |    PD: PC/MP address output multiplexer select
792 
  --                          |       |   |   |   |   |    |    |      PCR: register PC (program counter)
793 
  --                          |       |   |   |   |   |    |    |      |        MPR: register MP (memory pointer)
794 
  --                          |       |   |   |   |   |    |    |      |        |       P_OP: register P set/reset bit
795 
  --                          |       |   |   |   |   |    |    |      |        |       |       ALUOP: ALU operation
796 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       REGOP: registers load/increment/decrement etc.
797 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       RSEL: registers output multiplexer select
798 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       |
799 
  --                          |       |   |   |   |   |    |    |      |        |       |       |       |       |
800 
    case a is              -- DMUX    AI  VP  BR  EI  W    CLI  PD     PCR      MPR     P_OP    ALUOP   REGOP   RSEL
801 
      ------------------------------------
802 
      --            IMPLIED             --
803 
      ------------------------------------
804 
      -- BRK
805 
      when    BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- NOPs
806 
      when    BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1
807 
      when    BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1
808 
      when    BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ZRD_O; -- Z->S; SP-1; EI
809 
      when    BRK_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & SDW_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD
810 
      when    BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP
811 
      when    BRK_OP6 => q <= ORD_D &'0'&'1'&'0'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP
812 
 
813 
      -- NOP
814 
      when    NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
815 
 
816 
      -- CLC
817 
      when    CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI
818 
 
819 
      -- SEC
820 
      when    SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI
821 
 
822 
      -- CLI
823 
      when    CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI
824 
 
825 
      -- SEI
826 
      when    SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI
827 
 
828 
      -- CLV
829 
      when    CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI
830 
 
831 
      -- CLD
832 
      when    CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI
833 
 
834 
      -- SED
835 
      when    SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI
836 
 
837 
      -- TAX
838 
      when    TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & ARD_O; -- A->X; EI
839 
 
840 
      -- TXA
841 
      when    TXA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & XRD_O; -- X->A; EI
842 
 
843 
      -- TAY
844 
      when    TAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & ARD_O; -- A->Y; EI
845 
 
846 
      -- TYA
847 
      when    TYA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & YRD_O; -- Y->A; EI
848 
 
849 
      -- TXY
850 
      when    TXY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & XRD_O; -- X->Y; EI
851 
 
852 
      -- TYX
853 
      when    TYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & YRD_O; -- Y->X; EI
854 
 
855 
      -- TAZ
856 
      when    TAZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ZLD_R & ARD_O; -- A->Z; EI
857 
 
858 
      -- TZA
859 
      when    TZA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & ZRD_O; -- Z->A; EI
860 
 
861 
      -- TXS
862 
      when    TXS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S; EI
863 
 
864 
      -- TSX
865 
      when    TSX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S->X; EI
866 
 
867 
      -- INC A
868 
      when    INC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & ALD_R & ARD_O; -- A+1; EI
869 
 
870 
      -- DEC A
871 
      when    DEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & ALD_R & ARD_O; -- A-1; EI
872 
 
873 
      -- INX
874 
      when    INX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & XLD_R & XRD_O; -- X+1; EI
875 
 
876 
      -- DEX
877 
      when    DEX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & XLD_R & XRD_O; -- X-1; EI
878 
 
879 
      -- INY
880 
      when    INY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & YLD_R & YRD_O; -- Y+1; EI
881 
 
882 
      -- DEY
883 
      when    DEY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & YLD_R & YRD_O; -- Y-1; EI
884 
 
885 
      -- PHP
886 
      when    PHP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; EI
887 
 
888 
      -- PHA
889 
      when    PHA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1; EI
890 
 
891 
      -- PHX
892 
      when    PHX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; EI
893 
 
894 
      -- PHY
895 
      when    PHY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- X->S; SP-1; EI
896 
 
897 
      -- PHR
898 
      when    PHR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1;
899 
      when    PHR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1;
900 
      when    PHR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y->S; SP-1; EI
901 
 
902 
      -- PLP
903 
      when    PLP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
904 
      when    PLP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & NOP_R & EXT_O; -- S->P; EI
905 
 
906 
      -- PLA
907 
      when    PLA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
908 
      when    PLA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
909 
 
910 
      -- PLX
911 
      when    PLX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
912 
      when    PLX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- S->X; EI
913 
 
914 
      -- PLY
915 
      when    PLY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
916 
      when    PLY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- S->Y; EI
917 
 
918 
      -- PLR
919 
      when    PLR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
920 
      when    PLR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y;
921 
      when    PLR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X;
922 
      when    PLR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
923 
 
924 
      -- RTI
925 
      when    RTI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; MP=01XX (STACK)
926 
      when    RTI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; MEM->P; SP +1
927 
      when    RTI_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SZU_R & EXT_O; -- S->Z;
928 
      when    RTI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB PC->O; SP +1;
929 
      when    RTI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; SP +1;
930 
      when    RTI_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; MSB->MP; EI
931 
 
932 
      -- RTS
933 
      when    RTS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1
934 
      when    RTS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O;
935 
      when    RTS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1;
936 
      when    RTS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC
937 
      when    RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI
938 
 
939 
      -- ASL (A)
940 6 Valerio63 
      when    ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHL_A & ALD_R & ARD_O; -- A SHIFT LEFT; EI
941 4 Valerio63 
 
942 
      -- LSR (A)
943 6 Valerio63 
      when    LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHR_A & ALD_R & ARD_O; -- A SHIFT RIGHT; EI
944 4 Valerio63 
 
945 
      -- ROL (A)
946 6 Valerio63 
      when    ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROL_A & ALD_R & ARD_O; -- A ROTATE LEFT; EI
947 4 Valerio63 
 
948 
      -- ROR (A)
949 6 Valerio63 
      when    ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROR_A & ALD_R & ARD_O; -- A ROTATE RIGHT; EI
950 4 Valerio63 
 
951 
      -- XYX
952 
      when    XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
953 
      when    XYX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & YRD_O; -- Y->X;
954 
      when    XYX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ORD_O; -- O->Y; EI
955 
 
956 
      -- XAX
957 
      when    XAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
958 
      when    XAX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & ARD_O; -- A->X;
959 
      when    XAX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
960 
 
961 
      -- XAY
962 
      when    XAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & YRD_O; -- Y->O;
963 
      when    XAY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ARD_O; -- A->Y;
964 
      when    XAY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
965 
 
966 
      -- ISP
967 
      when    ISP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S lsb;
968 
      when    ISP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLM_R & ARD_O; -- A->S msb; EI
969 
 
970 
      -- TSP
971 
      when    TSP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S lsb ->X;
972 
      when    TSP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & SRM_O; -- S msb ->A; EI
973 
 
974 
 
975 
      ------------------------------------
976 
      --           IMMEDIATE            --
977 
      ------------------------------------
978 
      -- LDA #xx
979 
      when  IMLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MEM->A; PC +1; EI
980 
 
981 
      -- LDX #xx
982 
      when  IMLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MEM->X; PC +1; EI
983 
 
984 
      -- LDY #yy
985 
      when  IMLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MEM->Y; PC +1; EI
986 
 
987 
      -- ADC #xx (immediate)
988 6 Valerio63 
      when  IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; PC +1; EI
989 
      when  IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
990 4 Valerio63 
 
991 
      -- SBC #xx (immediate)
992 6 Valerio63 
      when  IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; PC +1; EI
993 
      when  IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
994 4 Valerio63 
 
995 
      -- CMP #xx (immediate)
996 6 Valerio63 
      when  IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI
997 4 Valerio63 
 
998 
      -- CPX #xx (immediate)
999 6 Valerio63 
      when  IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI
1000 4 Valerio63 
 
1001 
      -- CPY #xx (immediate)
1002 6 Valerio63 
      when  IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI
1003 4 Valerio63 
 
1004 
      -- AND #xx (immediate)
1005 
      when  IMAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A AND MEM -> A; PC +1;
1006 
 
1007 
      -- ORA #xx (immediate)
1008 
      when  IMORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A OR MEM -> A; PC +1;
1009 
 
1010 
      -- EOR #xx (immediate)
1011 
      when  IMEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A XOR MEM -> A; PC +1;
1012 
 
1013 
      -- BIT #xx (immediate)
1014 
      when  IMBRK_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & LDZ_P & BIT_A & NOP_R & ARD_O; -- A AND MEM; PC +1;
1015 
 
1016 
 
1017 
      ------------------------------------
1018 
      --           ZERO PAGE            --
1019 
      ------------------------------------
1020 
      -- LDA $xx (zero page)
1021 
      when  ZPLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1022 
      when  ZPLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1; EI
1023 
 
1024 
      -- LDX $xx (zero page)
1025 
      when  ZPLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1026 
      when  ZPLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1; EI
1027 
 
1028 
      -- LDY $xx (zero page)
1029 
      when  ZPLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1030 
      when  ZPLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI
1031 
 
1032 
      -- STA $xx (zero page)
1033 
      when  ZPSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1034 
      when  ZPSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1; EI
1035 
 
1036 
      -- STX $xx (zero page)
1037 
      when  ZPSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1038 
      when  ZPSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1; EI
1039 
 
1040 
      -- STY $xx (zero page)
1041 
      when  ZPSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1042 
      when  ZPSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1; EI
1043 
 
1044 
      -- STZ $xx (zero page)
1045 
      when  ZPSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1046 
      when  ZPSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1; EI
1047 
 
1048 
      -- ADC $xx (zero page)
1049 
      when  ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1050 6 Valerio63 
      when  ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
1051 
      when  ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1052 4 Valerio63 
 
1053 
      -- SBC $xx (zero page)
1054 
      when  ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1055 6 Valerio63 
      when  ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
1056 
      when  ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1057 4 Valerio63 
 
1058 
      -- CMP $xx (zeropage)
1059 
      when  ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1060 6 Valerio63 
      when  ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
1061 4 Valerio63 
 
1062 
      -- CPX $xx (zeropage)
1063 
      when  ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1064 6 Valerio63 
      when  ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI
1065 4 Valerio63 
 
1066 
      -- CPY $xx (zeropage)
1067 
      when  ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1068 6 Valerio63 
      when  ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI
1069 4 Valerio63 
 
1070 
      -- AND $xx (zeropage)
1071 
      when  ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1072 
      when  ZPAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM;  EI
1073 
 
1074 
      -- ORA $xx (zeropage)
1075 
      when  ZPORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1076 
      when  ZPORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM;  EI
1077 
 
1078 
      -- EOR $xx (zeropage)
1079 
      when  ZPEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1080 
      when  ZPEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM;  EI
1081 
 
1082 
      -- BIT $xx (zero page)
1083 
      when  ZPBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1084 
      when  ZPBIT_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1; EI
1085 
 
1086 
      -- ASL $xx (zero page)
1087 
      when  ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1088 
      when  ZPASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1089 6 Valerio63 
      when  ZPASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1090 4 Valerio63 
      when  ZPASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1091 
 
1092 
      -- LSR $xx (zero page)
1093 
      when  ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1094 
      when  ZPLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1095 6 Valerio63 
      when  ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1096 4 Valerio63 
      when  ZPLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1097 
 
1098 
      -- ROL $xx (zero page)
1099 
      when  ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1100 
      when  ZPROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1101 6 Valerio63 
      when  ZPROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1102 4 Valerio63 
      when  ZPROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1103 
 
1104 
      -- ROR $xx (zero page)
1105 
      when  ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1106 
      when  ZPROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1107 6 Valerio63 
      when  ZPROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1108 4 Valerio63 
      when  ZPROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1109 
 
1110 
      -- INC $xx (zero page)
1111 
      when  ZPINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1112 
      when  ZPINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1113 
      when  ZPINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1114 
      when  ZPINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1115 
 
1116 
      -- DEC $xx (zero page)
1117 
      when  ZPDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1118 
      when  ZPDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1119 
      when  ZPDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1120 
      when  ZPDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1121 
 
1122 
      -- TSB $xx (zero page)
1123 
      when  ZPTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1124 
      when  ZPTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1125 
      when  ZPTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1126 
      when  ZPTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O -> O
1127 
      when  ZPTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1128 
 
1129 
      -- TRB $xx (zero page)
1130 
      when  ZPTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1131 
      when  ZPTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
1132 
      when  ZPTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1133 
      when  ZPTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O -> O
1134 
      when  ZPTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
1135 
 
1136 
      ------------------------------------
1137 
      --          ZERO PAGE,X           --
1138 
      ------------------------------------
1139 
      -- LDA $xx,X (zero page indexed)
1140 
      when  ZXLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1141 
      when  ZXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1142 
      when  ZXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1143 
 
1144 
      -- LDY $xx,X (zero page indexed)
1145 
      when  ZXLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1146 
      when  ZXLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1147 
      when  ZXLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
1148 
 
1149 
      -- STA $xx,X (zero page indexed)
1150 
      when  ZXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1151 
      when  ZXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1152 
      when  ZXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1153 
 
1154 
      -- STY $xx,X (zero page indexed)
1155 
      when  ZXSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1156 
      when  ZXSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1157 
      when  ZXSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; EI
1158 
 
1159 
      -- STZ $xx,X (zero page indexed)
1160 
      when  ZXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1161 
      when  ZXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1162 
      when  ZXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; X->MEM; EI
1163 
 
1164 
      -- ADC $xx,X (zero page indexed)
1165 
      when  ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1166 
      when  ZXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1167 6 Valerio63 
      when  ZXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
1168 
      when  ZXADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); EI
1169 4 Valerio63 
 
1170 
      -- SBC $xx,X (zero page indexed)
1171 
      when  ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1172 
      when  ZXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1173 6 Valerio63 
      when  ZXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
1174 
      when  ZXSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); EI
1175 4 Valerio63 
 
1176 
      -- CMP $xx,X (zero page indexed)
1177 
      when  ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1178 
      when  ZXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1179 6 Valerio63 
      when  ZXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
1180 4 Valerio63 
 
1181 
      -- AND $xx,X (zero page indexed)
1182 
      when  ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1183 
      when  ZXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1184 
      when  ZXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM;  EI
1185 
 
1186 
      -- ORA $xx,X (zero page indexed)
1187 
      when  ZXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1188 
      when  ZXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1189 
      when  ZXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM;  EI
1190 
 
1191 
      -- EOR $xx,X (zero page indexed)
1192 
      when  ZXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1193 
      when  ZXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1194 
      when  ZXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM;  EI
1195 
 
1196 
      -- ASL $xx,X (zero page indexed)
1197 
      when  ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1198 
      when  ZXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X PC+1;
1199 
      when  ZXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1200 6 Valerio63 
      when  ZXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1201 4 Valerio63 
      when  ZXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1202 
 
1203 
      -- LSR $xx,X (zero page indexed)
1204 
      when  ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP
1205 
      when  ZXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1206 
      when  ZXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1207 6 Valerio63 
      when  ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1208 4 Valerio63 
      when  ZXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1209 
 
1210 
      -- ROL $xx,X (zero page indexed)
1211 
      when  ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1212 
      when  ZXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1213 
      when  ZXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1214 6 Valerio63 
      when  ZXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1215 4 Valerio63 
      when  ZXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1216 
 
1217 
      -- ROR $xx,X (zero page indexed)
1218 
      when  ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1219 
      when  ZXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1220 
      when  ZXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1221 6 Valerio63 
      when  ZXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1222 4 Valerio63 
      when  ZXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1223 
 
1224 
      -- INC $xx,X (zero page indexed)
1225 
      when  ZXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1226 
      when  ZXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1227 
      when  ZXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1228 
      when  ZXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1229 
      when  ZXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1230 
 
1231 
      -- DEC $xx,X (zero page indexed)
1232 
      when  ZXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1233 
      when  ZXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
1234 
      when  ZXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
1235 
      when  ZXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1236 
      when  ZXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1237 
 
1238 
      -- BIT $xx,X (zero page indexed)
1239 
      when  ZXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1240 
      when  ZXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
1241 
      when  ZXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A = A AND MEM;  EI
1242 
 
1243 
      ------------------------------------
1244 
      --          ZERO PAGE,Y           --
1245 
      ------------------------------------
1246 
      -- LDX $xx,Y (zero page indexed)
1247 
      when  ZYLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1248 
      when  ZYLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
1249 
      when  ZYLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
1250 
 
1251 
      -- STX $xx,Y (zero page indexed)
1252 
      when  ZYSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
1253 
      when  ZYSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
1254 
      when  ZYSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; EI
1255 
 
1256 
      ------------------------------------
1257 
      --           INDIRECT             --
1258 
      ------------------------------------
1259 
      -- JMP ($xxxx) (indirect)
1260 
      when  INJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1261 
      when  INJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1262 
      when  INJMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1
1263 
      when  INJMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC; O->PC; EI
1264 
 
1265 
      ------------------------------------
1266 
      --          INDIRECT,Y            --
1267 
      ------------------------------------
1268 
      -- LDA ($xx),Y (zeropage - indirect - indexed)
1269 
      when  IYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1270 
      when  IYLDA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1271 
      when  IYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1272 
      when  IYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- O->MP; (LSB POINTER)
1273 
      when  IYLDA_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1274 
 
1275 
      -- STA ($xx),Y (zeropage - indirect - indexed)
1276 
      when  IYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1277 
      when  IYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1278 
      when  IYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1279 
      when  IYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O->MP; (LSB POINTER)
1280 
      when  IYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1281 
 
1282 
      -- ADC ($xx),Y (zeropage - indirect - indexed)
1283 
      when  IYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1284 
      when  IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1285 
      when  IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1286 
      when  IYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1287 6 Valerio63 
      when  IYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1288 
      when  IYADC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1289 4 Valerio63 
 
1290 
      -- SBC ($xx),Y (zeropage - indirect - indexed)
1291 
      when  IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1292 
      when  IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1293 
      when  IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1294 
      when  IYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1295 6 Valerio63 
      when  IYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1296 
      when  IYSBC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAS); PC +1; EI
1297 4 Valerio63 
 
1298 
      -- CMP ($xx),Y (zeropage - indirect - indexed)
1299 
      when  IYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1300 
      when  IYCMP_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1301 
      when  IYCMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1302 6 Valerio63 
      when  IYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1303 
      when  IYCMP_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM;  A-MEM; EI
1304 4 Valerio63 
 
1305 
      -- AND ($xx),Y (zeropage - indirect - indexed)
1306 
      when  IYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1307 
      when  IYAND_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1308 
      when  IYAND_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1309 
      when  IYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1310 
      when  IYAND_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM; EI
1311 
 
1312 
      -- ORA ($xx),Y (zeropage - indirect - indexed)
1313 
      when  IYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1314 
      when  IYORA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1315 
      when  IYORA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1316 
      when  IYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1317 
      when  IYORA_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A = A OR MEM; EI
1318 
 
1319 
      -- EOR ($xx),Y (zeropage - indirect - indexed)
1320 
      when  IYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1321 
      when  IYEOR_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
1322 
      when  IYEOR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
1323 
      when  IYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
1324 
      when  IYEOR_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM; EI
1325 
 
1326 
      ------------------------------------
1327 
      --          INDIRECT,X            --
1328 
      ------------------------------------
1329 
      -- LDA ($xx,X) (zero page - indexed - indirect)
1330 
      when  IXLDA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1331 
      when  IXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1332 
      when  IXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1333 
      when  IXLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI=1
1334 
 
1335 
      -- STA ($xx,X) (zero page - indexed - indirect)
1336 
      when  IXSTA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1337 
      when  IXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1338 
      when  IXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1339 
      when  IXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- A->MEM; EI=1
1340 
 
1341 
      -- AND ($xx,X) (zero page - indexed - indirect)
1342 
      when  IXAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1343 
      when  IXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1344 
      when  IXAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1345 
      when  IXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; A=A AND MEM; EI=1
1346 
 
1347 
      -- ORA ($xx,X) (zero page - indexed - indirect)
1348 
      when  IXORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1349 
      when  IXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1350 
      when  IXORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1351 
      when  IXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; A=A OR MEM; EI=1
1352 
 
1353 
      -- EOR ($xx,X) (zero page - indexed - indirect)
1354 
      when  IXEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1355 
      when  IXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1356 
      when  IXEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1357 
      when  IXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1358 
 
1359 
      -- ADC ($xx,X) (zero page - indexed - indirect)
1360 
      when  IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1361 
      when  IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1362 
      when  IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1363 6 Valerio63 
      when  IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1364 
      when  IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1365 4 Valerio63 
 
1366 
      -- SBC ($xx,X) (zero page - indexed - indirect)
1367 
      when  IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1368 
      when  IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1369 
      when  IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1370 6 Valerio63 
      when  IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1371 
      when  IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1372 4 Valerio63 
 
1373 
      -- CMP ($xx,X) (zero page - indexed - indirect)
1374 
      when  IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
1375 
      when  IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
1376 
      when  IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
1377 6 Valerio63 
      when  IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
1378 4 Valerio63 
 
1379 
      -- JMP ($xxxx,X) (absolute indexed - indirect)
1380 
      when  IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1381 
      when  IXJMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1382 
      when  IXJMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1383 
      when  IXJMP_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1384 
      when  IXJMP_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1385 
 
1386 
      -- JSR ($xxxx,X) (absolute indexed - indirect)
1387 
      when  IXJSR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1388 
      when  IXJSR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
1389 
      when  IXJSR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
1390 
      when  IXJSR_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1391 
      when  IXJSR_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1392 
      when  IXJSR_OP5 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1393 
 
1394 
      ------------------------------------
1395 
      --           ABSOLUTE             --
1396 
      ------------------------------------
1397 
      -- LDA $xxxx (absolute)
1398 
      when  ABLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1399 
      when  ABLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1400 
      when  ABLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1
1401 
 
1402 
      -- LDX $xxxx (absolute)
1403 
      when  ABLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1404 
      when  ABLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1405 
      when  ABLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1
1406 
 
1407 
      -- LDY $xxxx (absolute)
1408 
      when  ABLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1409 
      when  ABLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1410 
      when  ABLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1
1411 
 
1412 
      -- STA $xxxx (absolute)
1413 
      when  ABSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1414 
      when  ABSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1415 
      when  ABSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1
1416 
 
1417 
      -- STX $xxxx (absolute)
1418 
      when  ABSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1419 
      when  ABSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1420 
      when  ABSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1
1421 
 
1422 
      -- STY $xxxx (absolute)
1423 
      when  ABSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1424 
      when  ABSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1425 
      when  ABSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1
1426 
 
1427 
      -- STZ $xxxx (absolute)
1428 
      when  ABSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1429 
      when  ABSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1430 
      when  ABSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1
1431 
 
1432 
      -- JMP $xxxx (absolute)
1433 
      when  ABJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
1434 
      when  ABJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1435 
 
1436 
      -- JSR $xxxx (absolute)
1437 
      when  ABJSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
1438 
      when  ABJSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
1439 
      when  ABJSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
1440 
      when  ABJSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
1441 
 
1442 
      -- BIT $xxxx (absolute)
1443 
      when  ABBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1444 
      when  ABBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1445 
      when  ABBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1
1446 
 
1447 
      -- ADC $xxxx (absolute)
1448 
      when  ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1449 
      when  ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1450 6 Valerio63 
      when  ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; EI
1451 
      when  ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1452 4 Valerio63 
 
1453 
      -- SBC $xxxx (absolute)
1454 
      when  ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1455 
      when  ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1456 6 Valerio63 
      when  ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; EI
1457 
      when  ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
1458 4 Valerio63 
 
1459 
      -- CMP $xxxx (absolute)
1460 
      when  ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1461 
      when  ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1462 6 Valerio63 
      when  ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI
1463 4 Valerio63 
 
1464 
      -- CPX $xxxx (absolute)
1465 
      when  ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1466 
      when  ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1467 6 Valerio63 
      when  ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI
1468 4 Valerio63 
 
1469 
      -- CPY $xxxx (absolute)
1470 
      when  ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1471 
      when  ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1472 6 Valerio63 
      when  ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI
1473 4 Valerio63 
 
1474 
      -- ORA $xxxx (absolute)
1475 
      when  ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1476 
      when  ABORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1477 
      when  ABORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- A=A OR MEM; EI
1478 
 
1479 
      -- AND $xxxx (absolute)
1480 
      when  ABAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1481 
      when  ABAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1482 
      when  ABAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A=A AND MEM; EI
1483 
 
1484 
      -- EOR $xxxx (absolute)
1485 
      when  ABEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1486 
      when  ABEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1487 
      when  ABEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A=A XOR MEM; EI
1488 
 
1489 
      -- ASL $xxxx (absolute)
1490 
      when  ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1491 
      when  ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1492 
      when  ABASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1493 6 Valerio63 
      when  ABASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
1494 4 Valerio63 
      when  ABASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1495 
 
1496 
      -- LSR $xxxx (absolute)
1497 
      when  ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1498 
      when  ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1499 
      when  ABLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1500 6 Valerio63 
      when  ABLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
1501 4 Valerio63 
      when  ABLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1502 
 
1503 
      -- ROL $xxxx (absolute)
1504 
      when  ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1505 
      when  ABROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1506 
      when  ABROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1507 6 Valerio63 
      when  ABROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
1508 4 Valerio63 
      when  ABROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1509 
 
1510 
      -- ROR $xxxx (absolute)
1511 
      when  ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1512 
      when  ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1513 
      when  ABROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1514 6 Valerio63 
      when  ABROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
1515 4 Valerio63 
      when  ABROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1516 
 
1517 
      -- INC $xxxx (absolute)
1518 
      when  ABINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1519 
      when  ABINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1520 
      when  ABINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1521 
      when  ABINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1522 
      when  ABINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1523 
 
1524 
      -- DEC $xxxx (absolute)
1525 
      when  ABDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1526 
      when  ABDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1527 
      when  ABDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1528 
      when  ABDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1529 
      when  ABDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1530 
 
1531 
      -- TSB $xxxx (absolute)
1532 
      when  ABTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1533 
      when  ABTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1534 
      when  ABTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1535 
      when  ABTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1536 
      when  ABTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O
1537 
      when  ABTSB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1538 
 
1539 
      -- TRB $xxxx (absolute)
1540 
      when  ABTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1541 
      when  ABTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
1542 
      when  ABTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
1543 
      when  ABTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
1544 
      when  ABTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O => O
1545 
      when  ABTRB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
1546 
 
1547 
      ------------------------------------
1548 
      --          ABSOLUTE,X            --
1549 
      ------------------------------------
1550 
      --                      DMUX: ALU operand #2 multiplexer
1551 
      --                      |       AI: effective address is indexed (X or Y)
1552 
      --                      |       |   VP: vector pull
1553 
      --                      |       |   |   BR: branch opcode
1554 
      --                      |       |   |   |   EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
1555 
      --                      |       |   |   |   |   W: read/write control
1556 
      --                      |       |   |   |   |   |    CLI: clear interrupt request
1557 
      --                      |       |   |   |   |   |    |    PD: PC/MP address output multiplexer select
1558 
      --                      |       |   |   |   |   |    |    |      PCR: register PC (program counter)
1559 
      --                      |       |   |   |   |   |    |    |      |        MPR: register MP (memory pointer)
1560 
      --                      |       |   |   |   |   |    |    |      |        |       P_OP: register P set/reset bit
1561 
      --                      |       |   |   |   |   |    |    |      |        |       |       ALUOP: ALU operation
1562 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       REGOP: registers load/increment/decrement etc.
1563 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       RSEL: registers output multiplexer select
1564 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       |
1565 
      --                      |       |   |   |   |   |    |    |      |        |       |       |       |       |
1566 
      --                   -- DMUX    AI  VP  BR  EI  W    CLI  PD     PCR      MPR     P_OP    ALUOP   REGOP   RSEL
1567 
      -- LDA $xxxx,X (absolute indexed)
1568 
      when  AXLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1569 
      when  AXLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1570 
      when  AXLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1571 
      when  AXLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1572 
 
1573 
      -- LDY $xxxx,X (absolute indexed)
1574 
      when  AXLDY_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1575 
      when  AXLDY_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1576 
      when  AXLDY_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y, MP_MSB+CARRY, EI
1577 
      when  AXLDY_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
1578 
 
1579 
      -- STA $xxxx,X (absolute indexed)
1580 
      when  AXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1581 
      when  AXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1582 
      when  AXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1583 
      when  AXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1584 
 
1585 
      -- STZ $xxxx,X (absolute indexed)
1586 
      when  AXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1587 
      when  AXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1588 
      when  AXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1589 
      when  AXSTZ_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI
1590 
 
1591 
      -- ADC $xxxx,X (absolute indexed)
1592 
      when  AXADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1593 
      when  AXADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1594 
      when  AXADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
1595 6 Valerio63 
      when  AXADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1596 
      when  AXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1597 4 Valerio63 
 
1598 
      -- SBC $xxxx,X (absolute indexed)
1599 
      when  AXSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1600 
      when  AXSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1601 
      when  AXSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
1602 6 Valerio63 
      when  AXSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1603 
      when  AXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1604 4 Valerio63 
 
1605 
      -- CMP $xxxx,X (absolute indexed)
1606 
      when  AXCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1607 
      when  AXCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1608 6 Valerio63 
      when  AXCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1609 
      when  AXCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
1610 4 Valerio63 
 
1611 
      -- INC $xxxx,X (absolute indexed)
1612 
      when  AXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1613 
      when  AXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1614 
      when  AXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1615 
      when  AXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1616 
      when  AXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
1617 
      when  AXINC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1618 
 
1619 
      -- DEC $xxxx,X (absolute indexed)
1620 
      when  AXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1621 
      when  AXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1622 
      when  AXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1623 
      when  AXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1624 
      when  AXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
1625 
      when  AXDEC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1626 
 
1627 
      -- ASL $xxxx,X (absolute indexed)
1628 
      when  AXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1629 
      when  AXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1630 
      when  AXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1631 
      when  AXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1632 6 Valerio63 
      when  AXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT
1633 4 Valerio63 
      when  AXASL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1634 
 
1635 
      -- LSR $xxxx,X (absolute indexed)
1636 
      when  AXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1637 
      when  AXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1638 
      when  AXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1639 
      when  AXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1640 6 Valerio63 
      when  AXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT
1641 4 Valerio63 
      when  AXLSR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1642 
 
1643 
      -- ROL $xxxx,X (absolute indexed)
1644 
      when  AXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1645 
      when  AXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1646 
      when  AXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1647 
      when  AXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1648 6 Valerio63 
      when  AXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT
1649 4 Valerio63 
      when  AXROL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1650 
 
1651 
      -- ROR $xxxx,X (absolute indexed)
1652 
      when  AXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1653 
      when  AXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1654 
      when  AXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1655 
      when  AXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
1656 6 Valerio63 
      when  AXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT
1657 4 Valerio63 
      when  AXROR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
1658 
 
1659 
      -- AND $xxxx,X (absolute indexed)
1660 
      when  AXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1661 
      when  AXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1662 
      when  AXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1663 
      when  AXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
1664 
 
1665 
      -- ORA $xxxx,X (absolute indexed)
1666 
      when  AXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1667 
      when  AXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1668 
      when  AXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1669 
      when  AXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
1670 
 
1671 
      -- EOR $xxxx,X (absolute indexed)
1672 
      when  AXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1673 
      when  AXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1674 
      when  AXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1675 
      when  AXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
1676 
 
1677 
      -- BIT $xxxx,X (absolute indexed)
1678 
      when  AXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1679 
      when  AXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
1680 
      when  AXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1681 
      when  AXBIT_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; EXT BIT A; EI
1682 
 
1683 
      ------------------------------------
1684 
      --          ABSOLUTE,Y            --
1685 
      ------------------------------------
1686 
      -- LDA $xxxx,X (absolute indexed)
1687 
      when  AYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1688 
      when  AYLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1689 
      when  AYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
1690 
      when  AYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
1691 
 
1692 
      -- LDX $xxxx,Y (absolute indexed)
1693 
      when  AYLDX_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1694 
      when  AYLDX_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1695 
      when  AYLDX_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; MP_MSB+CARRY, EI
1696 
      when  AYLDX_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
1697 
 
1698 
      -- STA $xxxx,Y (absolute indexed)
1699 
      when  AYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1700 
      when  AYSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1701 
      when  AYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
1702 
      when  AYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
1703 
 
1704 
      -- ADC $xxxx,Y (absolute indexed)
1705 
      when  AYADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1706 
      when  AYADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1707 
      when  AYADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
1708 6 Valerio63 
      when  AYADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
1709 
      when  AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
1710 4 Valerio63 
 
1711 
      -- SBC $xxxx,Y (absolute indexed)
1712 
      when  AYSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1713 
      when  AYSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1714 
      when  AYSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
1715 6 Valerio63 
      when  AYSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
1716 
      when  AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
1717 4 Valerio63 
 
1718 
      -- CMP $xxxx,Y (absolute indexed)
1719 
      when  AYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1720 
      when  AYCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1721 6 Valerio63 
      when  AYCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
1722 
      when  AYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
1723 4 Valerio63 
 
1724 
      -- AND $xxxx,Y (absolute indexed)
1725 
      when  AYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1726 
      when  AYAND_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1727 
      when  AYAND_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; MP_MSB+CARRY, EI
1728 
      when  AYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
1729 
 
1730 
      -- ORA $xxxx,Y (absolute indexed)
1731 
      when  AYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1732 
      when  AYORA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1733 
      when  AYORA_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; MP_MSB+CARRY, EI
1734 
      when  AYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P &  OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
1735 
 
1736 
      -- EOR $xxxx,Y (absolute indexed)
1737 
      when  AYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1738 
      when  AYEOR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
1739 
      when  AYEOR_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; MP_MSB+CARRY, EI
1740 
      when  AYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
1741 
 
1742 
      ------------------------------------
1743 
      --            RELATIVE            --
1744 
      ------------------------------------
1745 
      -- BRA xx
1746 
      when    BRA_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1747 
      when    BRA_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1748 
      when    BRA_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1749 
 
1750 
      -- BEQ xx
1751 
      when    BEQ_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1752 
      when    BEQ_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1753 
      when    BEQ_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1754 
 
1755 
      -- BNE xx
1756 
      when    BNE_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1757 
      when    BNE_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1758 
      when    BNE_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1759 
 
1760 
      -- BCC xx
1761 
      when    BCC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1762 
      when    BCC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1763 
      when    BCC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1764 
 
1765 
      -- BCS xx
1766 
      when    BCS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1767 
      when    BCS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1768 
      when    BCS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1769 
 
1770 
      -- BVC xx
1771 
      when    BVC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1772 
      when    BVC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1773 
      when    BVC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1774 
 
1775 
      -- BVS xx
1776 
      when    BVS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1777 
      when    BVS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1778 
      when    BVS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1779 
 
1780 
      -- BPL xx
1781 
      when    BPL_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1782 
      when    BPL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1783 
      when    BPL_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1784 
 
1785 
      -- BMI xx
1786 
      when    BMI_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
1787 
      when    BMI_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
1788 
      when    BMI_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
1789 
 
1790 
      when    others  => q <= NOP_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
1791 
    end case;
1792 
  end process;
1793 
end comb;
1794 
 
1795 
 

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