OpenCores
URL https://opencores.org/ocsvn/v6502/v6502/trunk

Subversion Repositories v6502

[/] [v6502/] [trunk/] [pre_dec.vhd] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 Valerio63
library IEEE;
2
use IEEE.std_logic_1164.all;  -- defines std_logic types
3
use IEEE.STD_LOGIC_unsigned.all;
4
use IEEE.STD_LOGIC_arith.all;
5
 
6
-- opcode decimal instructions and prefetch prediction logic
7
entity pre_dec is
8
  port(    op:  in STD_LOGIC_VECTOR(7 downto 0);
9
        fetch:  in STD_LOGIC;
10
           ei: out STD_LOGIC;
11
          dec: out STD_LOGIC
12
      );
13
end pre_dec;
14
 
15
architecture comb of pre_dec is
16
constant   NOP_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101010"; -- 0xEA NOP
17
constant   CLC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011000"; -- 0x18 CLC 0->C 
18
constant   SEC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111000"; -- 0x38 SEC 1->C
19
constant   CLI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011000"; -- 0x58 CLI 0->I
20
constant   SEI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111000"; -- 0x78 SEI 1->I
21
constant   CLV_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111000"; -- 0xB8 CLV 0->V
22
constant   CLD_OP: STD_LOGIC_VECTOR(7 downto 0) := "11011000"; -- 0xD8 CLD 0->D
23
constant   SED_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111000"; -- 0xF8 SED 1->D
24
constant   TAX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101010"; -- 0xAA TAX A->X
25
constant   TAY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101000"; -- 0xA8 TAY A->Y
26
constant   TXA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001010"; -- 0x8A TXA X->A
27
constant   TYA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011000"; -- 0x98 TYA Y->A
28
constant   TXY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011011"; -- 0x9B TXY X->Y
29
constant   TYX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111011"; -- 0xBB TYX Y->X
30
constant   TXS_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011010"; -- 0x9A TXS X->S
31
constant   TSX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111010"; -- 0xBA TSX S->X
32
constant   TAZ_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011011"; -- 0x1B TAZ A->Z
33
constant   TZA_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111011"; -- 0x3B TZA Z->A
34
constant   INX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101000"; -- 0xE8 INX X +1
35
constant   DEX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001010"; -- 0xCA DEX X -1
36
constant   INY_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001000"; -- 0xC8 INY Y +1
37
constant   DEY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001000"; -- 0x88 DEY Y -1
38
constant   ASL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00001010"; -- 0x0A ASL A  
39
constant   LSR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01001010"; -- 0x4A LSR A  
40
constant   ROL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00101010"; -- 0x2A ROL A  
41
constant   ROR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101010"; -- 0x6A ROR A  
42
constant  ADC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100001"; -- 0x61 ADC ($xx,X)
43
constant  ADC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110001"; -- 0x71 ADC ($xx),Y
44
constant  ADC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100101"; -- 0x65 ADC $xx
45
constant  ADC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110101"; -- 0x75 ADC $xx,X
46
constant  ADC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101001"; -- 0x69 ADC #xx
47
constant  ADC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111001"; -- 0x79 ADC $xxxx,Y
48
constant  ADC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111101"; -- 0x7D ADC $xxxx,X
49
constant  SBC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100001"; -- 0xE1 SBC ($xx,X)
50
constant  SBC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110001"; -- 0xF1 SBC ($xx),Y
51
constant  SBC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100101"; -- 0xE5 SBC $xx
52
constant  SBC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110101"; -- 0xF5 SBC $xx,X
53
constant  SBC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101001"; -- 0xE9 SBC #xx
54
constant  SBC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111001"; -- 0xF9 SBC $xxxx,Y
55
constant  SBC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111101"; -- 0xFD SBC $xxxx,X
56
 
57
signal eoi: STD_LOGIC;
58
begin
59
  process(op)
60
  begin
61
    case op is
62
      when NOP_OP  => eoi <= '1';
63
                      dec <= '0';
64
      when CLC_OP  => eoi <= '1';
65
                      dec <= '0';
66
      when SEC_OP  => eoi <= '1';
67
                      dec <= '0';
68
      when CLI_OP  => eoi <= '1';
69
                      dec <= '0';
70
      when SEI_OP  => eoi <= '1';
71
                      dec <= '0';
72
      when CLV_OP  => eoi <= '1';
73
                      dec <= '0';
74
      when CLD_OP  => eoi <= '1';
75
                      dec <= '0';
76
      when SED_OP  => eoi <= '1';
77
                      dec <= '0';
78
      when TAX_OP  => eoi <= '1';
79
                      dec <= '0';
80
      when TAY_OP  => eoi <= '1';
81
                      dec <= '0';
82
      when TAZ_OP  => eoi <= '1';
83
                      dec <= '0';
84
      when TXA_OP  => eoi <= '1';
85
                      dec <= '0';
86
      when TYA_OP  => eoi <= '1';
87
                      dec <= '0';
88
      when TXY_OP  => eoi <= '1';
89
                      dec <= '0';
90
      when TYX_OP  => eoi <= '1';
91
                      dec <= '0';
92
      when TZA_OP  => eoi <= '1';
93
                      dec <= '0';
94
      when TXS_OP  => eoi <= '1';
95
                      dec <= '0';
96
      when TSX_OP  => eoi <= '1';
97
                      dec <= '0';
98
      when INX_OP  => eoi <= '1';
99
                      dec <= '0';
100
      when DEX_OP  => eoi <= '1';
101
                      dec <= '0';
102
      when INY_OP  => eoi <= '1';
103
                      dec <= '0';
104
      when DEY_OP  => eoi <= '1';
105
                      dec <= '0';
106
      when ASL_OP  => eoi <= '1';
107
                      dec <= '0';
108
      when LSR_OP  => eoi <= '1';
109
                      dec <= '0';
110
      when ROL_OP  => eoi <= '1';
111
                      dec <= '0';
112
      when ROR_OP  => eoi <= '1';
113
                      dec <= '0';
114
      -- ADC/SBC
115
      when ADC1_OP => eoi <= '0';
116
                      dec <= '1';
117
      when ADC2_OP => eoi <= '0';
118
                      dec <= '1';
119
      when ADC3_OP => eoi <= '0';
120
                      dec <= '1';
121
      when ADC4_OP => eoi <= '0';
122
                      dec <= '1';
123
      when ADC5_OP => eoi <= '0';
124
                      dec <= '1';
125
      when ADC6_OP => eoi <= '0';
126
                      dec <= '1';
127
      when ADC7_OP => eoi <= '0';
128
                      dec <= '1';
129
      when SBC1_OP => eoi <= '0';
130
                      dec <= '1';
131
      when SBC2_OP => eoi <= '0';
132
                      dec <= '1';
133
      when SBC3_OP => eoi <= '0';
134
                      dec <= '1';
135
      when SBC4_OP => eoi <= '0';
136
                      dec <= '1';
137
      when SBC5_OP => eoi <= '0';
138
                      dec <= '1';
139
      when SBC6_OP => eoi <= '0';
140
                      dec <= '1';
141
      when SBC7_OP => eoi <= '0';
142
                      dec <= '1';
143
      when others  => eoi <= '0';
144
                      dec <= '0';
145
    end case;
146
  end process;
147
  ei <= eoi when fetch = '1' else '0';
148
end comb;
149
 
150
 
151
 
152
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.