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[/] [v65c816/] [trunk/] [BCDAdder.vhd] - Blame information for rev 4

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity bit_adder is
        port(
                A               : in std_logic;
                B               : in std_logic;
                CI              : in std_logic;
                S               : out std_logic;
                CO              : out std_logic
        );
end bit_adder;
 
architecture rtl of bit_adder is
 
begin
 
        S <= (not A and not B and     CI) or
                  (not A and     B and not CI) or
                  (    A and not B and not CI) or
                  (    A and     B and     CI);
 
        CO <= (not A and     B and     CI) or
                        (    A and not B and     CI) or
                        (    A and     B and not CI) or
                        (    A and     B and     CI);
 
end rtl;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity adder4 is
        port(
                A               : in std_logic_vector(3 downto 0);
                B               : in std_logic_vector(3 downto 0);
                CI              : in std_logic;
                S               : out std_logic_vector(3 downto 0);
                CO              : out std_logic
        );
end adder4;
 
architecture rtl of adder4 is
 
        component bit_adder is
        port(
                A               : in std_logic;
                B               : in std_logic;
                CI              : in std_logic;
                S               : out std_logic;
                CO              : out std_logic
        );
        end component;
 
        signal CO0, CO1, CO2 : std_logic;
 
begin
 
        b_add0: bit_adder port map (A(0), B(0), CI,  S(0), CO0);
        b_add1: bit_adder port map (A(1), B(1), CO0, S(1), CO1);
        b_add2: bit_adder port map (A(2), B(2), CO1, S(2), CO2);
        b_add3: bit_adder port map (A(3), B(3), CO2, S(3), CO);
 
end rtl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity BCDAdder is
        port(
                A               : in std_logic_vector(3 downto 0);
                B               : in std_logic_vector(3 downto 0);
                CI              : in std_logic;
 
                S               : out std_logic_vector(3 downto 0);
                CO              : out std_logic;
                VO              : out std_logic;
 
                ADD     : in std_logic;
                BCD     : in std_logic
        );
end BCDAdder;
 
architecture rtl of BCDAdder is
 
        signal B2               : std_logic_vector(3 downto 0);
        signal BIN_S    : std_logic_vector(3 downto 0);
        signal BIN_CO   : std_logic;
        signal BCD_B    : std_logic_vector(3 downto 0);
        signal BCD_CO   : std_logic;
 
begin
 
        B2 <= B xor (3 downto 0 => not ADD);
 
        bin_adder : entity work.adder4
        port map(
                A               => A,
                B               => B2,
                CI              => CI,
                S               => BIN_S,
                CO              => BIN_CO
        );
 
        BCD_CO <= (BIN_S(3) and BIN_S(2)) or (BIN_S(3) and BIN_S(1)) or (BIN_CO xor not ADD);
        BCD_B <= not ADD & ((BCD_CO and BCD) xor not ADD) & ((BCD_CO and BCD) xor not ADD) & not ADD;
 
        bcd_corr_adder : entity work.adder4
        port map(
                A               => BIN_S,
                B               => BCD_B,
                CI              => not ADD,
                S               => S
        );
 
        CO <= BIN_CO when BCD = '0' else BCD_CO xor not ADD;
        VO <= (not (A(3) xor B2(3))) and (A(3) xor BIN_S(3));
 
end rtl;

Line No.	Rev	Author	Line
1	2	Valerio63	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`library STD;`
4			`use IEEE.NUMERIC_STD.ALL;`
5			`library work;`
6
7			`entity bit_adder is`
8			`port(`
9			`A : in std_logic;`
10			`B : in std_logic;`
11			`CI : in std_logic;`
12			`S : out std_logic;`
13			`CO : out std_logic`
14			`);`
15			`end bit_adder;`
16
17			`architecture rtl of bit_adder is`
18
19			`begin`
20
21			`S <= (not A and not B and CI) or`
22			`(not A and B and not CI) or`
23			`( A and not B and not CI) or`
24			`( A and B and CI);`
25
26			`CO <= (not A and B and CI) or`
27			`( A and not B and CI) or`
28			`( A and B and not CI) or`
29			`( A and B and CI);`
30
31			`end rtl;`
32
33
34
35			`library IEEE;`
36			`use IEEE.STD_LOGIC_1164.ALL;`
37			`library STD;`
38			`use IEEE.NUMERIC_STD.ALL;`
39			`library work;`
40
41			`entity adder4 is`
42			`port(`
43			`A : in std_logic_vector(3 downto 0);`
44			`B : in std_logic_vector(3 downto 0);`
45			`CI : in std_logic;`
46			`S : out std_logic_vector(3 downto 0);`
47			`CO : out std_logic`
48			`);`
49			`end adder4;`
50
51			`architecture rtl of adder4 is`
52
53			`component bit_adder is`
54			`port(`
55			`A : in std_logic;`
56			`B : in std_logic;`
57			`CI : in std_logic;`
58			`S : out std_logic;`
59			`CO : out std_logic`
60			`);`
61			`end component;`
62
63			`signal CO0, CO1, CO2 : std_logic;`
64
65			`begin`
66
67			`b_add0: bit_adder port map (A(0), B(0), CI, S(0), CO0);`
68			`b_add1: bit_adder port map (A(1), B(1), CO0, S(1), CO1);`
69			`b_add2: bit_adder port map (A(2), B(2), CO1, S(2), CO2);`
70			`b_add3: bit_adder port map (A(3), B(3), CO2, S(3), CO);`
71
72			`end rtl;`
73
74
75			`library IEEE;`
76			`use IEEE.STD_LOGIC_1164.ALL;`
77			`library STD;`
78			`use IEEE.NUMERIC_STD.ALL;`
79			`library work;`
80
81			`entity BCDAdder is`
82			`port(`
83			`A : in std_logic_vector(3 downto 0);`
84			`B : in std_logic_vector(3 downto 0);`
85			`CI : in std_logic;`
86
87			`S : out std_logic_vector(3 downto 0);`
88			`CO : out std_logic;`
89			`VO : out std_logic;`
90
91			`ADD : in std_logic;`
92			`BCD : in std_logic`
93			`);`
94			`end BCDAdder;`
95
96			`architecture rtl of BCDAdder is`
97
98			`signal B2 : std_logic_vector(3 downto 0);`
99			`signal BIN_S : std_logic_vector(3 downto 0);`
100			`signal BIN_CO : std_logic;`
101			`signal BCD_B : std_logic_vector(3 downto 0);`
102			`signal BCD_CO : std_logic;`
103
104			`begin`
105
106			`B2 <= B xor (3 downto 0 => not ADD);`
107
108			`bin_adder : entity work.adder4`
109			`port map(`
110			`A => A,`
111			`B => B2,`
112			`CI => CI,`
113			`S => BIN_S,`
114			`CO => BIN_CO`
115			`);`
116
117			`BCD_CO <= (BIN_S(3) and BIN_S(2)) or (BIN_S(3) and BIN_S(1)) or (BIN_CO xor not ADD);`
118			`BCD_B <= not ADD & ((BCD_CO and BCD) xor not ADD) & ((BCD_CO and BCD) xor not ADD) & not ADD;`
119
120			`bcd_corr_adder : entity work.adder4`
121			`port map(`
122			`A => BIN_S,`
123			`B => BCD_B,`
124			`CI => not ADD,`
125			`S => S`
126			`);`
127
128			`CO <= BIN_CO when BCD = '0' else BCD_CO xor not ADD;`
129			`VO <= (not (A(3) xor B2(3))) and (A(3) xor BIN_S(3));`
130
131			`end rtl;`

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[/] [v65c816/] [trunk/] [BCDAdder.vhd] - Blame information for rev 4