OpenCores
URL https://opencores.org/ocsvn/v65c816/v65c816/trunk

Subversion Repositories v65c816

[/] [v65c816/] [trunk/] [addrmux.vhd] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 Valerio63
library IEEE;
2
use IEEE.std_logic_1164.all;  -- defines std_logic types
3
use IEEE.STD_LOGIC_unsigned.all;
4
use IEEE.STD_LOGIC_arith.all;
5
 
6
-- 16 bit two-way multiplexer
7
entity addrmux is
8
  port(  sel:  in STD_LOGIC_VECTOR(2 downto 0);
9
           a:  in STD_LOGIC_VECTOR(23 downto 0);
10
           b:  in STD_LOGIC_VECTOR(23 downto 0);
11
                        dbr:  in STD_LOGIC_VECTOR(7 downto 0);
12
           s:  in STD_LOGIC_VECTOR(15 downto 0);
13
                         xr:  in STD_LOGIC_VECTOR(15 downto 0);
14
                         yr:  in STD_LOGIC_VECTOR(15 downto 0);
15
           y: out STD_LOGIC_VECTOR(23 downto 0)
16
      );
17
end addrmux;
18
 
19
architecture comb of addrmux is
20
constant ADPC: STD_LOGIC_VECTOR(2 downto 0) := "000";  -- select PC
21
constant ADMP: STD_LOGIC_VECTOR(2 downto 0) := "001";  -- select MP
22
constant ADSP: STD_LOGIC_VECTOR(2 downto 0) := "010";  -- select SP
23
constant ADDI: STD_LOGIC_VECTOR(2 downto 0) := "011";  -- select Direct
24
constant ADXR: STD_LOGIC_VECTOR(2 downto 0) := "100";  -- select X register
25
constant ADYR: STD_LOGIC_VECTOR(2 downto 0) := "101";  -- select Y register
26
constant ADNP: STD_LOGIC_VECTOR(2 downto 0) := "000";  -- no operation (PC)
27
begin
28
  process(sel,a,b,s,xr,yr,dbr)
29
  begin
30
    case sel is
31
      when ADPC   => y <= a;                             -- program counter
32
      when ADMP   => y <= b;                             -- memory data pointer
33
      when ADSP   => y <= "00000000" & s;                -- stack address space
34
      when ADDI   => y <= "00000000" & b(15 downto 0);   -- direct address space
35
                when ADXR   => y <= dbr & xr;                      -- DBR\X register
36
                when ADYR   => y <= dbr & yr;                      -- DBR\Y register
37
      when others => y <= a;
38
    end case;
39
  end process;
40
end comb;
41
 
42
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.