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[/] [v65c816/] [trunk/] [ar.vhd] - Blame information for rev 3

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library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
 
-- 16 bit accumulator register "A"
entity ar is
  port(       clk:  in STD_LOGIC;
            fwait:  in STD_LOGIC;
             size:  in STD_LOGIC;
           ld_lsb:  in STD_LOGIC;
           ld_msb:  in STD_LOGIC;
            ld_mul_lsb:  in STD_LOGIC;
                            d:  in STD_LOGIC;
                  end_count: out STD_LOGIC;
              din:  in STD_LOGIC_VECTOR(15 downto 0);
                         mul_lsb:  in STD_LOGIC_VECTOR(15 downto 0);
             dout: out STD_LOGIC_VECTOR(15 downto 0)
      );
end ar;
 
architecture rtl of ar is
signal reg: STD_LOGIC_VECTOR(15 downto 0);
signal op:  STD_LOGIC_VECTOR(3 downto 0);
begin
  op <= ld_mul_lsb & d & ld_msb & ld_lsb;
  process(clk)
    begin
      if (clk'event and clk = '1') then
        if fwait = '1' then
          reg <= reg;
        else
                    if size = '1' then
                                 case op is
                                        when   "0001" => reg(7 downto 0) <= din(7 downto 0);             -- load lsb
                                               reg(15 downto 8) <= reg(15 downto 8);
                                        when   "0010" => reg(15 downto 8) <= din(7 downto 0);            -- load msb
                                                                                  reg(7 downto 0) <= reg(7 downto 0);
                                        when   "0011" => reg(7 downto 0) <= din(7 downto 0);             -- load msb & lsb                                                
                                               reg(15 downto 8) <= reg(15 downto 8);
                                        when   "0100" => reg <= reg - "0000000000000001";                -- decrement
                                        when   "1000" => reg <= mul_lsb;                                 -- load multiplication lsb result
                                        when others   => reg <= reg;
                                 end case;
                         else
                                 case op is
                                        when   "0001" => reg(7 downto 0) <= din(7 downto 0);             -- load lsb
                                                                                 reg(15 downto 8) <= reg(15 downto 8);
                                        when   "0010" => reg(15 downto 8) <= din(7 downto 0);            -- load msb
                                                                                 reg(7 downto 0) <= reg(7 downto 0);
                                        when   "0011" => reg <= din;                                     -- load msb & lsb                                              
                                        when   "0100" => reg <= reg - "0000000000000001";                -- decrement
                                        when   "1000" => reg <= mul_lsb;                                 -- load multiplication lsb result
                                        when others  => reg <= reg;
                                 end case;
          end if;
        end if;
      end if;
  end process;
  dout <= reg;
 
  -- used for MVN/MVP instructions
  process(reg)
  begin
                if reg = "1111111111111111" then
                        end_count <= '1';
                else
                        end_count <= '0';
                end if;
  end process;
end rtl;
 
 

Line No.	Rev	Author	Line
1	2	Valerio63	`library IEEE;`
2			`use IEEE.std_logic_1164.all; -- defines std_logic types`
3			`use IEEE.STD_LOGIC_unsigned.all;`
4			`use IEEE.STD_LOGIC_arith.all;`
5
6			`-- 16 bit accumulator register "A"`
7			`entity ar is`
8			`port( clk: in STD_LOGIC;`
9			`fwait: in STD_LOGIC;`
10			`size: in STD_LOGIC;`
11			`ld_lsb: in STD_LOGIC;`
12			`ld_msb: in STD_LOGIC;`
13			`ld_mul_lsb: in STD_LOGIC;`
14			`d: in STD_LOGIC;`
15			`end_count: out STD_LOGIC;`
16			`din: in STD_LOGIC_VECTOR(15 downto 0);`
17			`mul_lsb: in STD_LOGIC_VECTOR(15 downto 0);`
18			`dout: out STD_LOGIC_VECTOR(15 downto 0)`
19			`);`
20			`end ar;`
21
22			`architecture rtl of ar is`
23			`signal reg: STD_LOGIC_VECTOR(15 downto 0);`
24			`signal op: STD_LOGIC_VECTOR(3 downto 0);`
25			`begin`
26			`op <= ld_mul_lsb & d & ld_msb & ld_lsb;`
27			`process(clk)`
28			`begin`
29			`if (clk'event and clk = '1') then`
30			`if fwait = '1' then`
31			`reg <= reg;`
32			`else`
33			`if size = '1' then`
34			`case op is`
35			`when "0001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb`
36			`reg(15 downto 8) <= reg(15 downto 8);`
37			`when "0010" => reg(15 downto 8) <= din(7 downto 0); -- load msb`
38			`reg(7 downto 0) <= reg(7 downto 0);`
39			`when "0011" => reg(7 downto 0) <= din(7 downto 0); -- load msb & lsb`
40			`reg(15 downto 8) <= reg(15 downto 8);`
41			`when "0100" => reg <= reg - "0000000000000001"; -- decrement`
42			`when "1000" => reg <= mul_lsb; -- load multiplication lsb result`
43			`when others => reg <= reg;`
44			`end case;`
45			`else`
46			`case op is`
47			`when "0001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb`
48			`reg(15 downto 8) <= reg(15 downto 8);`
49			`when "0010" => reg(15 downto 8) <= din(7 downto 0); -- load msb`
50			`reg(7 downto 0) <= reg(7 downto 0);`
51			`when "0011" => reg <= din; -- load msb & lsb`
52			`when "0100" => reg <= reg - "0000000000000001"; -- decrement`
53			`when "1000" => reg <= mul_lsb; -- load multiplication lsb result`
54			`when others => reg <= reg;`
55			`end case;`
56			`end if;`
57			`end if;`
58			`end if;`
59			`end process;`
60			`dout <= reg;`
61
62			`-- used for MVN/MVP instructions`
63			`process(reg)`
64			`begin`
65			`if reg = "1111111111111111" then`
66			`end_count <= '1';`
67			`else`
68			`end_count <= '0';`
69			`end if;`
70			`end process;`
71			`end rtl;`
72
73

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[/] [v65c816/] [trunk/] [ar.vhd] - Blame information for rev 3