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[/] [v65c816/] [trunk/] [cpufsm.vhd] - Blame information for rev 4

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library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
 
-- CPU FSM main state machine
entity cpufsm is
  port(      clk:  in STD_LOGIC;
             clr:  in STD_LOGIC;
           fwait:  in STD_LOGIC;
            ireq:  in STD_LOGIC;
             aim:  in STD_LOGIC;
          bcarry:  in STD_LOGIC;
          icarry:  in STD_LOGIC;
              p1:  in STD_LOGIC_VECTOR(2 downto 0);
            e_ei:  in STD_LOGIC;
           mc_ei:  in STD_LOGIC;
          addsub:  in STD_LOGIC;
        dec_mode:  in STD_LOGIC;
           fetch: out STD_LOGIC;
         op_sync: out STD_LOGIC;
             pci: out STD_LOGIC;
              pq: out STD_LOGIC_VECTOR(2 downto 0);
              fb: out STD_LOGIC;
              od: out STD_LOGIC;
          mc_nop: out STD_LOGIC
      );
end cpufsm;
 
architecture rtl of cpufsm is
type states is (s0,s1,s2,s3,s4,s5,s6);
attribute ENUM_ENCODING:STRING;
attribute ENUM_ENCODING of states: type is "000000001 000000010 000000100 000001000 000010000 000100000 001000000";  -- one hot encoding for all states
signal present,nxt:states;
begin
  process(clk)
  begin
    if (clk'event and clk = '1') then
      if fwait = '1' then
        present <= present;
      else
        present <= nxt;
      end if;
    end if;
  end process;
 
  process(present,ireq,bcarry,icarry,p1,e_ei,mc_ei,aim,clr,addsub,dec_mode)
  begin
    case present is
      -- reset
      when s0 =>
      fetch <= '0';
      op_sync <= '0';
      pci <= '0';
      pq <= "000";
      fb <= '1';                              -- force BRK                              
      od <= '1';                              -- clear microcode sequencer
      mc_nop <= '0';
      if clr = '1' then
        nxt <= s0;
      else
        nxt <= s2;
      end if;
 
      -- fetch opcode
      when s1 =>
      pq <= "000";
      if ireq = '1' then                      -- if interrupt request
        od <= '0';
                  fetch <= '0';
        fb <= '0';
        pci <= '0';                           -- PC doesn't increment
        op_sync <= '0';
        mc_nop <= '1';                        -- stop microcode execution
        nxt <= s6;                            -- goto s6
      else
        od <= '1';                            -- clear microcode sequencer
        fetch <= '1';                         -- fetch opcode
                  fb <= '0';
        pci <= '1';                           -- PC increment
        if addsub = '1'then                   -- if ADD/SUB opcode may require an extra cycle for DAA/DAS adjustement
          op_sync <= '0';
          mc_nop <= '0';
          nxt <= s5;                          -- goto s5
        else
          if e_ei = '1' then                  -- if end of instruction is reached on fetch 
            mc_nop <= '1';
            if clr = '1' then                 -- if reset
              op_sync <= '0';
              nxt <= s0;                      -- goto reset 
            else
              op_sync <= '1';                 -- remain in this state to fetch a new opcode
              nxt <= s1;
            end if;
          else
            mc_nop <= '0';
            op_sync <= '0';                   -- goto s2
            nxt <= s2;
          end if;
        end if;
      end if;
 
      -- wait until end of instruction
      when s2 =>
      fetch <= '0';
      pq <= p1;
      fb <= '0';
      od <= '0';
      mc_nop <= '0';
      pci <= '0';
      if aim = '1' then                     -- opcode with indexed mode
        op_sync <= '0';
        nxt <= s3;
      else
        if mc_ei = '1' then                 -- if end of instruction is reached 
          if clr = '1' then
            op_sync <= '0';
            nxt <= s0;
          else
            op_sync <= '1';
            nxt <= s1;
          end if;
        else
            op_sync <= '0';
            nxt <= s2;
        end if;
      end if;
 
      when s3 =>                            -- opcode with absolute indexed mode
      fetch <= '0';
      pq <= p1;
      fb <= '0';
      od <= '0';
      pci <= '0';
      if mc_ei = '1' then                   -- if end of instruction is reached 
        if icarry = '0' then
          mc_nop <= '1';
          if clr = '1' then
            op_sync <= '0';
            nxt <= s0;
          else
            op_sync <= '1';
            nxt <= s1;
          end if;
        else
          op_sync <= '0';
          mc_nop <= '0';
          nxt <= s4;
        end if;
      else
        op_sync <= '0';
        mc_nop <= '0';
        nxt <= s3;
      end if;
 
      when s4 =>                            -- opcode with absolute indexed mode: add carry to msb PC
      fetch <= '0';
      pq <= p1;
      fb <= '0';
      od <= '0';
      pci <= '0';
      if clr = '1' then
        mc_nop <= '0';
        op_sync <= '0';
        nxt <= s0;
      else
        mc_nop <= '1';
        op_sync <= '1';
        nxt <= s1;
      end if;
 
      -- ADD/SUB decimal adjustement extra cycle
      when s5 =>
      fetch <= '0';
      pq <= p1;
      fb <= '0';
      od <= '0';
      pci <= '0';
      if mc_ei = '1' then
        if dec_mode = '0' then
          mc_nop <= '1';
        else
          mc_nop <= '0';
        end if;
        if clr = '1' then
          op_sync <= '0';
          nxt <= s0;
        else
          op_sync <= '1';
          nxt <= s1;
        end if;
      else
        mc_nop <= '0';
        op_sync <= '0';
        nxt <= s5;
      end if;
 
      when s6 =>
      pq <= "000";
      od <= '1';                            -- clear microcode sequencer
      fetch <= '0';
      fb <= '1';                            -- force load BRK to opcode register 
      pci <= '0';                           -- PC doesn't increment
      op_sync <= '1';
      mc_nop <= '0';
      nxt <= s2;                            -- goto s2
 
      -- illegal state covering
      when others =>
      fetch <= '0';
      op_sync <= '0';
      pci <= '0';
      pq <= "000";
      fb <= '0';
      od <= '1';
      mc_nop <= '0';
      nxt <= s0;
 
    end case;
  end process;
end rtl;
 
 

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[/] [v65c816/] [trunk/] [cpufsm.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	Valerio63	`library IEEE;`
2			`use IEEE.std_logic_1164.all; -- defines std_logic types`
3			`use IEEE.STD_LOGIC_unsigned.all;`
4			`use IEEE.STD_LOGIC_arith.all;`
5
6			`-- CPU FSM main state machine`
7			`entity cpufsm is`
8			`port( clk: in STD_LOGIC;`
9			`clr: in STD_LOGIC;`
10			`fwait: in STD_LOGIC;`
11			`ireq: in STD_LOGIC;`
12			`aim: in STD_LOGIC;`
13			`bcarry: in STD_LOGIC;`
14			`icarry: in STD_LOGIC;`
15			`p1: in STD_LOGIC_VECTOR(2 downto 0);`
16			`e_ei: in STD_LOGIC;`
17			`mc_ei: in STD_LOGIC;`
18			`addsub: in STD_LOGIC;`
19			`dec_mode: in STD_LOGIC;`
20			`fetch: out STD_LOGIC;`
21			`op_sync: out STD_LOGIC;`
22			`pci: out STD_LOGIC;`
23			`pq: out STD_LOGIC_VECTOR(2 downto 0);`
24			`fb: out STD_LOGIC;`
25			`od: out STD_LOGIC;`
26			`mc_nop: out STD_LOGIC`
27			`);`
28			`end cpufsm;`
29
30			`architecture rtl of cpufsm is`
31			`type states is (s0,s1,s2,s3,s4,s5,s6);`
32			`attribute ENUM_ENCODING:STRING;`
33			`attribute ENUM_ENCODING of states: type is "000000001 000000010 000000100 000001000 000010000 000100000 001000000"; -- one hot encoding for all states`
34			`signal present,nxt:states;`
35			`begin`
36			`process(clk)`
37			`begin`
38			`if (clk'event and clk = '1') then`
39			`if fwait = '1' then`
40			`present <= present;`
41			`else`
42			`present <= nxt;`
43			`end if;`
44			`end if;`
45			`end process;`
46
47			`process(present,ireq,bcarry,icarry,p1,e_ei,mc_ei,aim,clr,addsub,dec_mode)`
48			`begin`
49			`case present is`
50			`-- reset`
51			`when s0 =>`
52			`fetch <= '0';`
53			`op_sync <= '0';`
54			`pci <= '0';`
55			`pq <= "000";`
56			`fb <= '1'; -- force BRK`
57			`od <= '1'; -- clear microcode sequencer`
58			`mc_nop <= '0';`
59			`if clr = '1' then`
60			`nxt <= s0;`
61			`else`
62			`nxt <= s2;`
63			`end if;`
64
65			`-- fetch opcode`
66			`when s1 =>`
67			`pq <= "000";`
68			`if ireq = '1' then -- if interrupt request`
69			`od <= '0';`
70			`fetch <= '0';`
71			`fb <= '0';`
72			`pci <= '0'; -- PC doesn't increment`
73			`op_sync <= '0';`
74			`mc_nop <= '1'; -- stop microcode execution`
75			`nxt <= s6; -- goto s6`
76			`else`
77			`od <= '1'; -- clear microcode sequencer`
78			`fetch <= '1'; -- fetch opcode`
79			`fb <= '0';`
80			`pci <= '1'; -- PC increment`
81			`if addsub = '1'then -- if ADD/SUB opcode may require an extra cycle for DAA/DAS adjustement`
82			`op_sync <= '0';`
83			`mc_nop <= '0';`
84			`nxt <= s5; -- goto s5`
85			`else`
86			`if e_ei = '1' then -- if end of instruction is reached on fetch`
87			`mc_nop <= '1';`
88			`if clr = '1' then -- if reset`
89			`op_sync <= '0';`
90			`nxt <= s0; -- goto reset`
91			`else`
92			`op_sync <= '1'; -- remain in this state to fetch a new opcode`
93			`nxt <= s1;`
94			`end if;`
95			`else`
96			`mc_nop <= '0';`
97			`op_sync <= '0'; -- goto s2`
98			`nxt <= s2;`
99			`end if;`
100			`end if;`
101			`end if;`
102
103			`-- wait until end of instruction`
104			`when s2 =>`
105			`fetch <= '0';`
106			`pq <= p1;`
107			`fb <= '0';`
108			`od <= '0';`
109			`mc_nop <= '0';`
110			`pci <= '0';`
111			`if aim = '1' then -- opcode with indexed mode`
112			`op_sync <= '0';`
113			`nxt <= s3;`
114			`else`
115			`if mc_ei = '1' then -- if end of instruction is reached`
116			`if clr = '1' then`
117			`op_sync <= '0';`
118			`nxt <= s0;`
119			`else`
120			`op_sync <= '1';`
121			`nxt <= s1;`
122			`end if;`
123			`else`
124			`op_sync <= '0';`
125			`nxt <= s2;`
126			`end if;`
127			`end if;`
128
129			`when s3 => -- opcode with absolute indexed mode`
130			`fetch <= '0';`
131			`pq <= p1;`
132			`fb <= '0';`
133			`od <= '0';`
134			`pci <= '0';`
135			`if mc_ei = '1' then -- if end of instruction is reached`
136			`if icarry = '0' then`
137			`mc_nop <= '1';`
138			`if clr = '1' then`
139			`op_sync <= '0';`
140			`nxt <= s0;`
141			`else`
142			`op_sync <= '1';`
143			`nxt <= s1;`
144			`end if;`
145			`else`
146			`op_sync <= '0';`
147			`mc_nop <= '0';`
148			`nxt <= s4;`
149			`end if;`
150			`else`
151			`op_sync <= '0';`
152			`mc_nop <= '0';`
153			`nxt <= s3;`
154			`end if;`
155
156			`when s4 => -- opcode with absolute indexed mode: add carry to msb PC`
157			`fetch <= '0';`
158			`pq <= p1;`
159			`fb <= '0';`
160			`od <= '0';`
161			`pci <= '0';`
162			`if clr = '1' then`
163			`mc_nop <= '0';`
164			`op_sync <= '0';`
165			`nxt <= s0;`
166			`else`
167			`mc_nop <= '1';`
168			`op_sync <= '1';`
169			`nxt <= s1;`
170			`end if;`
171
172			`-- ADD/SUB decimal adjustement extra cycle`
173			`when s5 =>`
174			`fetch <= '0';`
175			`pq <= p1;`
176			`fb <= '0';`
177			`od <= '0';`
178			`pci <= '0';`
179			`if mc_ei = '1' then`
180			`if dec_mode = '0' then`
181			`mc_nop <= '1';`
182			`else`
183			`mc_nop <= '0';`
184			`end if;`
185			`if clr = '1' then`
186			`op_sync <= '0';`
187			`nxt <= s0;`
188			`else`
189			`op_sync <= '1';`
190			`nxt <= s1;`
191			`end if;`
192			`else`
193			`mc_nop <= '0';`
194			`op_sync <= '0';`
195			`nxt <= s5;`
196			`end if;`
197
198			`when s6 =>`
199			`pq <= "000";`
200			`od <= '1'; -- clear microcode sequencer`
201			`fetch <= '0';`
202			`fb <= '1'; -- force load BRK to opcode register`
203			`pci <= '0'; -- PC doesn't increment`
204			`op_sync <= '1';`
205			`mc_nop <= '0';`
206			`nxt <= s2; -- goto s2`
207
208			`-- illegal state covering`
209			`when others =>`
210			`fetch <= '0';`
211			`op_sync <= '0';`
212			`pci <= '0';`
213			`pq <= "000";`
214			`fb <= '0';`
215			`od <= '1';`
216			`mc_nop <= '0';`
217			`nxt <= s0;`
218
219			`end case;`
220			`end process;`
221			`end rtl;`
222
223