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Valerio63 |
library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 16 bit memory pointer address register
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entity mpr is
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port( clk: in STD_LOGIC;
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fwait: in STD_LOGIC;
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dbr_ld: in STD_LOGIC;
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c: in STD_LOGIC;
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fc: in STD_LOGIC_VECTOR(4 downto 0);
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din_l: in STD_LOGIC_VECTOR(7 downto 0);
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din_h: in STD_LOGIC_VECTOR(7 downto 0);
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dbr: in STD_LOGIC_VECTOR(7 downto 0);
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dr: in STD_LOGIC_VECTOR(15 downto 0);
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op: in STD_LOGIC_VECTOR(15 downto 0);
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xr: in STD_LOGIC_VECTOR(15 downto 0);
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yr: in STD_LOGIC_VECTOR(15 downto 0);
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sr: in STD_LOGIC_VECTOR(15 downto 0);
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v: in STD_LOGIC_VECTOR(7 downto 0);
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dout: out STD_LOGIC_VECTOR(23 downto 0)
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);
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end mpr;
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architecture rtl of mpr is
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constant NOP_M: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation
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constant LSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- load lsb
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constant MSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- load msb
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constant INC_M: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- increment
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constant DEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- decrement
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constant VEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- load vector
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constant ZPL_M: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- load ZEROPAGE
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constant ALL_M: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- load all 16 bit register
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constant ICC_M: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- increment MSB with carry
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constant DOX_M: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- add D + offset + X
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constant DOY_M: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- add D + offset + Y
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constant AOS_M: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- add S + offset
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constant ABX_M: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- add opr+X
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constant ABY_M: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- add opr+Y
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constant ADX_M: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- add X
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constant ADY_M: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- add Y
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constant MHB_M: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- load high byte
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constant AOY_M: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- add opr+Y and concatenates SBR
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signal reg: STD_LOGIC_VECTOR(23 downto 0);
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begin
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process(clk)
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begin
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if (clk'event and clk = '1') then
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if fwait = '1' then
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reg <= reg;
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else
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if dbr_ld = '1' then -- on every opcode fetch the high byte of MPR is loaded with DBR value
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reg(23 downto 16) <= dbr;
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end if;
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case fc is
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when LSB_M => reg(7 downto 0) <= din_l; reg(23 downto 8) <= reg(23 downto 8); -- load LSB (bit 7..0)
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when MSB_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= reg(7 downto 0); reg(23 downto 16) <= reg(23 downto 16); -- load MSB (bit 15..8)
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when ALL_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= din_l; reg(23 downto 16) <= reg(23 downto 16); -- load LSB/MSB (bit 15..0)
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when INC_M => reg <= reg +1; -- increment 24 bit
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when DEC_M => reg <= reg -1; -- decrement 24 bit
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when VEC_M => reg <= "0000000011111111" & v; -- 0x00FFXX load vector
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when ZPL_M => reg(15 downto 0) <= dr + ("00000000" & din_l); -- 0x00XXXX zeropage operation (D + 0x0000XX)
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when ICC_M => reg(15 downto 8) <= reg(15 downto 8) + c; -- increment MSB for indexed addressing mode
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when DOX_M => reg(15 downto 0) <= dr + ("00000000" & din_l) + xr; -- D+offset+X
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when DOY_M => reg(15 downto 0) <= dr + ("00000000" & din_l) + yr; -- D+offset+Y
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when AOS_M => reg(15 downto 0) <= sr + ("00000000" & din_h); reg(23 downto 16) <= "00000000"; -- S+offset
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when ABX_M => reg(15 downto 0) <= din_h & op(7 downto 0) + xr; -- +O+X
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when ABY_M => reg(15 downto 0) <= din_h & op(7 downto 0) + yr; -- +O+Y
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when ADX_M => reg <= reg + ("00000000" & xr); -- +X (24 bit SUM)
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when ADY_M => reg <= reg + ("00000000" & yr); -- +Y (24 bit SUM)
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when MHB_M => reg(23 downto 16) <= din_h; reg(15 downto 0) <= op; -- load high byte (bit 23..16)
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when AOY_M => reg <= (dbr & op) + ("00000000" & yr); -- O+Y (24 bit SUM)
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when others => reg <= reg;
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end case;
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end if;
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end if;
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end process;
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dout <= reg;
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end rtl;
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