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[/] [v65c816/] [trunk/] [pcr.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 16 bit program counter register "PC"
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entity pcr is
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  port(       clk:  in STD_LOGIC;
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                i:  in STD_LOGIC;
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            fwait:  in STD_LOGIC;
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                     brk_op:  in STD_LOGIC;                            -- forced BRK (by interrupt request) 
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                 branch_flg:  in STD_LOGIC;                            -- branch flag   
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                      mov_f:  in STD_LOGIC;                            -- MVN/MVP end transfer
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               fc:  in STD_LOGIC_VECTOR(3 downto 0);
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             din1:  in STD_LOGIC_VECTOR(7 downto 0);
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             din2:  in STD_LOGIC_VECTOR(15 downto 0);
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             dout: out STD_LOGIC_VECTOR(15 downto 0)
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      );
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end pcr;
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architecture rtl of pcr is
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constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PC no operation
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constant LSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PC load lsb
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constant MSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- PC load msb
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constant INC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- PC increment by 1
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constant LOD_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- PC load lsb\msb  (used by JMP\JSR instructions)
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constant LML_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- PC load lsb\msb from oper register (used for JML\JSL instructions)
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constant IN2_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- PC = PC +2 (BRK opcode)
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constant DE3_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- PC = PC -3 (MVN/MVP opcodes)
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constant BRA_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- PC branch
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constant BRL_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- PC branch long 
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signal reg: STD_LOGIC_VECTOR(15 downto 0);
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begin
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  process(clk)
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    begin
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      if (clk'event and clk = '1') then
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        if fwait = '1' then
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          reg <= reg;
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        else
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          if i = '1' then
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            reg <= reg +1;
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          else
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            case fc is
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              when LSB_P  => reg(7 downto 0) <= din1; reg(15 downto 8) <= reg(15 downto 8);
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              when MSB_P  => reg(15 downto 8) <= din1; reg(7 downto 0) <= reg(7 downto 0);
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              when INC_P  => reg <= reg +1;
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              when LOD_P  => reg(15 downto 8) <= din1; reg(7 downto 0) <= din2(7 downto 0);
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              when BRA_P  =>
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                                    if branch_flg = '1' THEN                                                                     -- if branch taken
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                                       if din1(7) = '0' THEN                                                                     -- if branch forward
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                                                           reg <= reg + "0000000000000001" + ("00000000" & din1);
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                                                 else                                                                                      -- if branch backwards
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                                                           reg <= reg + "0000000000000001" - ("00000000" & (0 - din1));
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                                                 end if;
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                                         else                                                                                         -- if branch not taken  
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                   reg <= reg + "0000000000000001";
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                          end if;
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              when BRL_P  =>
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                          if din1(7) = '0' THEN                                                                        -- if branch forward
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                                                           reg <= reg + "0000000000000001" + (din1 & din2(7 downto 0));
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                                         else                                                                                         -- if branch backwards
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                                                           reg <= reg + "0000000000000001" - (0 - (din1 & din2(7 downto 0)));
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                                         end if;
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              when LML_P  => reg <= din2;
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              when IN2_P  =>
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                                          if brk_op = '1' then                                                                   -- if BRK opcode PC=PC+2
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                                                 reg <= reg +1;                                                                  -- PC already incremented by 1 by cpufsm
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                                                    else
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                                                                reg <= reg;
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                                                         end if;
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              when DE3_P  =>
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                                          if mov_f = '0' then                                                                    -- if MVN/MVP transfer not finished 
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                                                 reg <= reg - "0000000000000011";
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                                                         else
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                                                                reg <= reg;
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                                                         end if;
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              when NOP_P  => reg <= reg;
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              when others => reg <= reg;
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            end case;
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          end if;
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        end if;
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      end if;
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  end process;
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  dout <= reg;
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end rtl;
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