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[/] [v65c816/] [trunk/] [pr.vhd] - Blame information for rev 2

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1 2 Valerio63 
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8 bit processor status register P
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-- NV1BDIZC
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-- 76543210
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-- ||||||||
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-- ||||||||--- C/E = carry/borrow flag (emulation bit: 1 = emulation mode, 0 = native mode)
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-- |||||||---- Z = zero flag
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-- ||||||----- I = interrupt mask
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-- |||||------ D = decimal/binary alu mode
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-- ||||------- B/X = index reg. select (1 = 8 bit, 0 = 16 bit) (B Break: 0 on stack after interrupt if E emulation mode = 1)
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-- |||-------- M = memory/acc. select (1 = 8 bit, 0 = 16 bit) (always 1 if E = 1)
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-- ||--------- V = overflow flag
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-- |---------- N = negative flag
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entity pr is
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  port(      clk:  in STD_LOGIC;                        -- clock
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             clr:  in STD_LOGIC;                        -- clear
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           fwait:  in STD_LOGIC;
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               n:  in STD_LOGIC;                        -- N input
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               v:  in STD_LOGIC;                        -- V input
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               z:  in STD_LOGIC;                        -- Z input
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               c:  in STD_LOGIC;                        -- C input
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                     mpy_z:  in STD_LOGIC;                        -- Z input from multiplier
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                     mpy_n:  in STD_LOGIC;                        -- N input from multiplier
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             swi:  in STD_LOGIC;                        -- software interrupt (BRK/COP opcode flag)
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          acr_in:  in STD_LOGIC;                        -- auxiliary carry in
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              fc:  in STD_LOGIC_VECTOR(4 downto 0);     -- function code
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             din:  in STD_LOGIC_VECTOR(7 downto 0);     -- input
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            dout: out STD_LOGIC_VECTOR(7 downto 0);     -- output
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         acr_out: out STD_LOGIC;                        -- auxiliary carry out
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                             em: out STD_LOGIC;                        -- emulation (1)/native mode (0)
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                         two_op: out STD_LOGIC                         -- two byte instruction
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      );
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end pr;
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architecture rtl of pr is
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constant NOP_P: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- PR no operation
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constant PLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- PR load
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constant FLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- NZ load
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constant FLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- NZC load
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constant FLV_P: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- NVZC load
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constant SEC_P: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- 1 => C
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constant CLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- 0 => C
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constant SEI_P: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- 1 => I
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constant CLI_P: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- 0 => I
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constant SED_P: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- 1 => D
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constant CLD_P: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- 0 => D
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constant CLV_P: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- 0 => V
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constant AUC_P: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- auc => ACR
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constant HAC_P: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- hold ACR
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constant SID_P: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- 1 => I/D
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constant LDZ_P: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- Z load
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constant XCE_P: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- E => C; C => E
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constant SEP_P: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- P = P OR din
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constant REP_P: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- P = P AND not din
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constant WDM_P: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- 1 => op_exp;
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constant WDC_P: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- 0 => op_exp;
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constant FLW_P: STD_LOGIC_VECTOR(4 downto 0) := "10101"; -- NZ load, 0 -> op_exp
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constant MUF_P: STD_LOGIC_VECTOR(4 downto 0) := "10110"; -- Z load from unsigned multplier
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constant MSF_P: STD_LOGIC_VECTOR(4 downto 0) := "10111"; -- NZ load from unsigned multplier
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signal    reg: STD_LOGIC_VECTOR(7 downto 0);
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signal    acr: STD_LOGIC;                                                      -- carry/borrow used for effective address calculation
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signal     eb: STD_LOGIC;                                                      -- emulation/native bit
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signal op_exp: STD_LOGIC;                                                      -- two opcode bit
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signal  swint: STD_LOGIC;                                                      -- bit 4 saved on stack when BRK/COP
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begin
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  process(clk)
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    begin
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      if (clk'event and clk = '1') then
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        if fwait = '1' then
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          reg <= reg;
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        else
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          if clr = '1' then
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            reg <= "00110100";                                                 -- on reset M,X,I = '1'
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            acr <= '0';
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                                eb <= '1';                                                         -- on reset set emulation mode
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                                op_exp <= '0';
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          else
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            case fc is
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              when PLD_P  => reg    <= din;                                    -- load NVMXDIZC
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when FLD_P  => reg    <= n & reg(6 downto 2) & z & reg(0);       -- load NZ
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when FLC_P  => reg    <= n & reg(6 downto 2) & z & c;            -- load NZC
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when FLV_P  => reg <= n & v & reg(5 downto 2) & z & c;           -- load NVZC
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                             acr <= '0';
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              when SEC_P  => reg    <= reg or  "00000001";                     -- 1 => C
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when CLC_P  => reg    <= reg and "11111110";                     -- 0 => C
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when CLI_P  => reg    <= reg and "11111011";                     -- 0 => I
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when SED_P  => reg    <= reg or  "00001000";                     -- 1 => D
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when CLD_P  => reg    <= reg and "11110111";                     -- 0 => D
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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                                  when LDZ_P  => reg(1) <= z;                                      -- z => Z
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                             reg(7 downto 2) <= reg(7 downto 2);
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                                            reg(0) <= reg(0);
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when SEI_P  => reg(7 downto 3) <= reg(7 downto 3);
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                             reg(2) <= '1';                                    -- 1 => I
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                             reg(1 downto 0) <= reg(1 downto 0);
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when SID_P  => reg(7 downto 4) <= reg(7 downto 4);               -- set I and clear D decimal flag (used by interrupt sequence)
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                             reg(3) <= '0';                                    -- 0 -> D
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                             reg(2) <= '1';                                    -- 1 => I
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                             reg(1 downto 0) <= reg(1 downto 0);
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when CLV_P  => reg    <= reg and "10111111";                     -- 0 => V
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                             acr    <= acr;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when AUC_P  => acr    <= acr_in;                                 -- store auxiliary carry (ACR)
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                             reg    <= reg;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when HAC_P  => acr    <= acr;                                    -- holds auxiliary carry (ACR)
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                             reg    <= reg;
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when XCE_P  => eb     <= reg(0);                                 -- exchange C <=> E (switch emulation/native mode)
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                             reg(0) <= eb;
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                             reg(7 downto 1) <= reg(7 downto 1);
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                             acr    <= '0';
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                                                                          op_exp <= op_exp;
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                                  when SEP_P  => reg    <= reg or din;                             -- SEP
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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                                  when REP_P  => reg    <= reg and (not din);                      -- REP
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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                                  when WDM_P  => op_exp <= '1';                                    -- set two byte opcode
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                             reg    <= reg;
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                  when WDC_P  => op_exp <= '0';                                    -- clear two byte opcode
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                             reg    <= reg;
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                             acr    <= '0';
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                                                                          eb     <= eb;
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              when FLW_P  => reg    <= n & reg(6 downto 2) & z & reg(0);       -- load NZ, 0 => op_exp
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= '0';
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              when MUF_P  => reg    <= "00" & reg(5 downto 2) & mpy_z & '0';    -- load Z from multiplier, C/VN=0
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when MSF_P  => reg    <= mpy_n & '0' & reg(5 downto 2) & mpy_z & '0';  -- load NZ from multiplier, CV=0
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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              when others => reg    <= reg;
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                             acr    <= '0';
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                                                                          eb     <= eb;
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                                                                          op_exp <= op_exp;
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            end case;
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                                if eb = '1' then                                                   -- in emulation mode M/X are always set to '1'
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                                   reg(5 downto 4) <= "11";
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                                end if;
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          end if;
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        end if;
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      end if;
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  end process;
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  process(fc,reg(4),eb,swi)
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  begin
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    if fc = SID_P then
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            if eb = '0' then
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                    swint <= reg(4);
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                 else
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               swint <= swi;                                                        -- when emulation mode is set the bit 4 reflects BRK opcode (pushed on stack)
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            end if;
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         else
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       swint <= reg(4);
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    end if;
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  end process;
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  dout(7 downto 5) <= reg(7 downto 5);
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  dout(4) <= swint;                                                            -- save BRK/COP B="1" on stack if emulation mode
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  dout(3 downto 0) <= reg(3 downto 0);
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  acr_out <= acr;
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  em <= eb;
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  two_op <= op_exp;
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end rtl;
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