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[/] [v65c816/] [trunk/] [pre_dec.vhd] - Blame information for rev 2

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1 2 Valerio63 
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- opcode decimal instructions and prefetch prediction logic
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entity pre_dec is
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  port(    op:  in STD_LOGIC_VECTOR(7 downto 0);
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        fetch:  in STD_LOGIC;
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           ei: out STD_LOGIC;
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          dec: out STD_LOGIC
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      );
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end pre_dec;
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architecture comb of pre_dec is
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constant   NOP_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101010"; -- 0xEA NOP
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constant   CLC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011000"; -- 0x18 CLC 0->C
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constant   SEC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111000"; -- 0x38 SEC 1->C
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constant   CLI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011000"; -- 0x58 CLI 0->I
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constant   SEI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111000"; -- 0x78 SEI 1->I
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constant   CLV_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111000"; -- 0xB8 CLV 0->V
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constant   CLD_OP: STD_LOGIC_VECTOR(7 downto 0) := "11011000"; -- 0xD8 CLD 0->D
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constant   SED_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111000"; -- 0xF8 SED 1->D
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constant   TAX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101010"; -- 0xAA TAX A->X
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constant   TAY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101000"; -- 0xA8 TAY A->Y
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constant   TXA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001010"; -- 0x8A TXA X->A
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constant   TYA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011000"; -- 0x98 TYA Y->A
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constant   TXY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011011"; -- 0x9B TXY X->Y
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constant   TYX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111011"; -- 0xBB TYX Y->X
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constant   TXS_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011010"; -- 0x9A TXS X->S
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constant   TSX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111010"; -- 0xBA TSX S->X
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constant   TCD_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011011"; -- 0x5B TCD C->D
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constant   TDC_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111011"; -- 0x7B TDC D->C
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constant   TCS_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011011"; -- 0x1B TCS C->S
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constant   TSC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111011"; -- 0x3B TSC S->C
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constant   INX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101000"; -- 0xE8 INX X +1
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constant   DEX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001010"; -- 0xCA DEX X -1
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constant   INY_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001000"; -- 0xC8 INY Y +1
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constant   DEY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001000"; -- 0x88 DEY Y -1
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constant   ASL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00001010"; -- 0x0A ASL A
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constant   LSR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01001010"; -- 0x4A LSR A
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constant   ROL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00101010"; -- 0x2A ROL A
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constant   ROR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101010"; -- 0x6A ROR A
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constant   XCE_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111011"; -- 0xFB XCE E<->C
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constant   XBA_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101011"; -- 0xEB XBA (swap A/B)
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constant   WDM_OP: STD_LOGIC_VECTOR(7 downto 0) := "01000010"; -- 0x42 WDM
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constant  ADC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100001"; -- 0x61 ADC ($xx,X)
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constant  ADC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110001"; -- 0x71 ADC ($xx),Y
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constant  ADC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100101"; -- 0x65 ADC $xx
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constant  ADC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110101"; -- 0x75 ADC $xx,X
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constant  ADC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101001"; -- 0x69 ADC #xx
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constant  ADC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111001"; -- 0x79 ADC $xxxx,Y
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constant  ADC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111101"; -- 0x7D ADC $xxxx,X
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constant  SBC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100001"; -- 0xE1 SBC ($xx,X)
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constant  SBC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110001"; -- 0xF1 SBC ($xx),Y
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constant  SBC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100101"; -- 0xE5 SBC $xx
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constant  SBC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110101"; -- 0xF5 SBC $xx,X
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constant  SBC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101001"; -- 0xE9 SBC #xx
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constant  SBC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111001"; -- 0xF9 SBC $xxxx,Y
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constant  SBC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111101"; -- 0xFD SBC $xxxx,X
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signal eoi: STD_LOGIC;
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begin
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  process(op)
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  begin
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    case op is
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      when NOP_OP  => eoi <= '1';
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                      dec <= '0';
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      when CLC_OP  => eoi <= '1';
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                      dec <= '0';
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      when SEC_OP  => eoi <= '1';
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                      dec <= '0';
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      when CLI_OP  => eoi <= '1';
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                      dec <= '0';
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      when SEI_OP  => eoi <= '1';
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                      dec <= '0';
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      when CLV_OP  => eoi <= '1';
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                      dec <= '0';
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      when CLD_OP  => eoi <= '1';
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                      dec <= '0';
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      when SED_OP  => eoi <= '1';
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                      dec <= '0';
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      when TAX_OP  => eoi <= '1';
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                      dec <= '0';
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      when TAY_OP  => eoi <= '1';
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                      dec <= '0';
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      when TCD_OP  => eoi <= '1';
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                      dec <= '0';
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      when TDC_OP  => eoi <= '1';
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                      dec <= '0';
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      when TXA_OP  => eoi <= '1';
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                      dec <= '0';
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      when TYA_OP  => eoi <= '1';
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                      dec <= '0';
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      when TXY_OP  => eoi <= '1';
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                      dec <= '0';
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      when TYX_OP  => eoi <= '1';
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                      dec <= '0';
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      when TXS_OP  => eoi <= '1';
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                      dec <= '0';
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      when TSX_OP  => eoi <= '1';
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                      dec <= '0';
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      when TCS_OP  => eoi <= '1';
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                      dec <= '0';
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      when TSC_OP  => eoi <= '1';
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                      dec <= '0';
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      when INX_OP  => eoi <= '1';
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                      dec <= '0';
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      when DEX_OP  => eoi <= '1';
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                      dec <= '0';
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      when INY_OP  => eoi <= '1';
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                      dec <= '0';
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      when DEY_OP  => eoi <= '1';
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                      dec <= '0';
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      when ASL_OP  => eoi <= '1';
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                      dec <= '0';
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      when LSR_OP  => eoi <= '1';
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                      dec <= '0';
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      when ROL_OP  => eoi <= '1';
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                      dec <= '0';
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      when ROR_OP  => eoi <= '1';
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                      dec <= '0';
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      when XCE_OP  => eoi <= '1';
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                      dec <= '0';
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      when XBA_OP  => eoi <= '1';
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                      dec <= '0';
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      when WDM_OP  => eoi <= '1';
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                      dec <= '0';
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      -- ADC/SBC
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      when ADC1_OP => eoi <= '0';
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                      dec <= '1';
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      when ADC2_OP => eoi <= '0';
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                      dec <= '1';
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--      when ADC3_OP => eoi <= '0';
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--                      dec <= '1';
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      when ADC4_OP => eoi <= '0';
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                      dec <= '1';
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      when ADC5_OP => eoi <= '0';
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                      dec <= '1';
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      when ADC6_OP => eoi <= '0';
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                      dec <= '1';
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      when ADC7_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC1_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC2_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC3_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC4_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC5_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC6_OP => eoi <= '0';
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                      dec <= '1';
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      when SBC7_OP => eoi <= '0';
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                      dec <= '1';
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      when others  => eoi <= '0';
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                      dec <= '0';
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    end case;
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  end process;
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  ei <= eoi when fetch = '1' else '0';
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end comb;
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