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[/] [v65c816/] [trunk/] [spr.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8/16 bit stack pointer register "S"
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entity spr is
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  port(   clk:  in STD_LOGIC;
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          clr:  in STD_LOGIC;
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        fwait:  in STD_LOGIC;
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                     em:  in STD_LOGIC;
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         ld_l:  in STD_LOGIC;
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         ld_h:  in STD_LOGIC;
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            u:  in STD_LOGIC;
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            d:  in STD_LOGIC;
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          din:  in STD_LOGIC_VECTOR(15 downto 0);
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         dout: out STD_LOGIC_VECTOR(15 downto 0)
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      );
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end spr;
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architecture rtl of spr is
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constant SP_6502_VALUE:    STD_LOGIC_VECTOR(15 downto 0)  := "0000000111111111"; -- $01FF standard 6502 stack pointer
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signal   x: STD_LOGIC_VECTOR(3 downto 0);
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signal reg: STD_LOGIC_VECTOR(15 downto 0);
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begin
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  x(0) <= ld_l;
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  x(1) <= ld_h;
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  x(2) <= u;
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  x(3) <= d;
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  process(clk)
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    begin
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      if (clk'event and clk = '1') then
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        if fwait = '1' then
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          reg <= reg;
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        else
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          if clr = '1' then
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            reg <= SP_6502_VALUE;
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          else
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                           if em = '0' then                                                -- native mode (S full 16 bit) 
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                                        case x is
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                                          when "0001"  => reg(7 downto 0)  <= din(7 downto 0);
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                                                                                        reg(15 downto 8) <= reg(15 downto 8);
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                                          when "0010"  => reg(15 downto 8) <= din(7 downto 0);
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                                                                                        reg(7 downto 0)  <= reg(7 downto 0);
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                                          when "0011"  => reg <= din;
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                                          when "0100"  => reg <= reg + 1;
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                                          when "1000"  => reg <= reg - 1;
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                                          when others  => reg <= reg;
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                                        end case;
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                                else                                                            -- emulation mode (S is forced to 0x01XX)
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                                        case x is
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                                          when "0001"  => reg(7 downto 0) <= din(7 downto 0);
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                                          when "0011"  => reg(7 downto 0) <= din(7 downto 0);
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                                          when "0100"  => reg(7 downto 0) <= reg(7 downto 0) + 1;
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                                          when "1000"  => reg(7 downto 0) <= reg(7 downto 0) - 1;
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                                          when others  => reg(7 downto 0) <= reg(7 downto 0);
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                                        end case;
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                                   reg(15 downto 8) <= SP_6502_VALUE(15 downto 8);
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                                end if;
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          end if;
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        end if;
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      end if;
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  end process;
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  dout <= reg;
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end rtl;
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