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---------------------------------------------------------------------------------------
-- CN3 glue logic                                                                    -- 
-- autoinitializing logic                                                            -- 
-- full synchronous logic design                                                     --                                                    
-- full VHDL-RTL style coding design                                                 --
-- target: ALTERA CPLD MAX II EPM570F256C5                                           --
-- project by Valerio Venturi ELMA Riva del Garda (TN) Italy (2009)                  --
-- Date: 16/10/2009                                                                  --
---------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
 
-- global architecture 
entity v65c816_bench is
end v65c816_bench;
 
use work.v65c816;
 
architecture behavior of v65c816_bench is
  component v65c816 is
          port(     clk0:    in STD_LOGIC;                       -- PHASE0 clock input
                                         res:    in STD_LOGIC;                       -- reset input
                                         irq:    in STD_LOGIC;                       -- interrupt request input
                                         nmi:    in STD_LOGIC;                       -- not maskable interrupt input
                                         rdy:    in STD_LOGIC;                       -- wait state input (read/write)
                                          rw:   out STD_LOGIC;                       -- read/write out
                                         vpa:   out STD_LOGIC;                       -- vpa
                                         vda:   out STD_LOGIC;                       -- vda
                                          vp:   out STD_LOGIC;                       -- vector pull
                                         ope:   out STD_LOGIC;                       -- microcode end 
                                                e:   out STD_LOGIC;                       -- emulation (1)/native mode (0) 
                                                m:   out STD_LOGIC;                       -- M status   
                                                x:   out STD_LOGIC;                       -- X status   
                                 op_exp:   out STD_LOGIC;                                 -- two byte instruction running
                                        addr:   out STD_LOGIC_VECTOR(23 downto 0);   -- 16 bit address bus out
                                data_in:    in STD_LOGIC_VECTOR(7 downto 0);    -- 8 bit input data bus
                          data_out:   out STD_LOGIC_VECTOR(7 downto 0);    -- 8 bit output data bus
                                  a_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit A register
                                  x_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit X register
                                  y_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Y register
                                  s_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit S register
                                 op_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Operand register         
                                  p_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit P register
                                  k_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit K register
                                  b_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit B register
                                  o_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit Opcode register
                                  mcode:   out STD_LOGIC_VECTOR(3 downto 0)     --  4 bit microcode sequence register
                        );
  end component;
 
  signal clk0,res,irq,nmi,rdy,rw,vpa,vda,vp,ope,e,m,x,op_exp:             STD_LOGIC;
  signal addr:                                                            STD_LOGIC_VECTOR(23 downto 0);
  signal data_in:                                                         STD_LOGIC_VECTOR(7 downto 0);
  signal data_out:                                                        STD_LOGIC_VECTOR(7 downto 0);
  signal a_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit A register
  signal x_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit X register
  signal y_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Y register
  signal s_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit S register
  signal op_reg:                                                          STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Operand register      
  signal p_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit P register
  signal k_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit K register
  signal b_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit B register
  signal o_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit Opcode register
  signal mcode:                                                           STD_LOGIC_VECTOR(3 downto 0);    --  4 bit microcode sequence register
 
  constant clk_period: time := 50 ns;
  --signal clock: STD_LOGIC := '0';
 
  begin
  u1:   v65c816 port map(
                         clk0,
                                                                 res,
                                                                 irq,
                                                                 nmi,
                                                                 rdy,
                                                                 rw,
                                                                 vpa,
                                                                 vda,
                                                                 vp,
                                                                 ope,
                                                                 e,
                                                                 m,
                                                                 x,
                                                                 op_exp,
                         addr,
                                                                 data_in,
                                                                 data_out,
                         a_reg,
                                             x_reg,
                                             y_reg,
                                             s_reg,
                                             op_reg,
                                             p_reg,
                                             k_reg,
                                             b_reg,
                                             o_reg,
                                             mcode
                                                 );
 
 
  tst_clock: process                                       -- 10 MHZ (period 100 ns) clock generation
             variable clktmp: STD_LOGIC := '0';
             begin
               clktmp := not clktmp;
               clk0 <= clktmp;
             wait for 50 ns;
             end process;
 
  stimulus:  process
             begin
               -- signal initialization before reset
               res <= '0';
                              irq <= '1';
                              nmi <= '1';
                              rdy <= '1';
               wait for 350 ns;
 
               -- device reset completed
               res <= '1';
               wait for 600 ns;
               data_in <= "00000000";                      -- fetch lsb reset PC vector 0x00
               wait for 50 ns;
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11000001";                      -- fetch msb reset PC vector 0xc1 (0xc100)
               wait for 70 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "00011000";                      -- CLC
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "11111011";                      -- XCE
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";                      -- XCE execution
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "11000010";                      -- REP #%00100000
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "00100000";                      -- $20
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "10101001";                      -- LDA #$0000
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "00000000";                      -- $00
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "00000000";                      -- $00
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               wait for 50 ns;
               data_in <= "00011000";                      -- CLC
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "01101001";                      -- ADC #$0001
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "00000001";                      -- $01
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "00000000";                      -- $00
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "00111000";                      -- SEC
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101001";                      -- SBC #0002
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "00000010";                      -- $02
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "00000000";                      -- $00
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
               data_in <= "ZZZZZZZZ";
               wait for 50 ns;
               data_in <= "11101010";                      -- NOP
               wait for 50 ns;
               data_in <= "ZZZZZZZZ";
 
 
               --wait for 1000000 ns;
               wait;
            end process;
end behavior;
 
 
 

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[/] [v65c816/] [trunk/] [v65c816_bench.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	Valerio63	`---------------------------------------------------------------------------------------`
2			`-- CN3 glue logic --`
3			`-- autoinitializing logic --`
4			`-- full synchronous logic design --`
5			`-- full VHDL-RTL style coding design --`
6			`-- target: ALTERA CPLD MAX II EPM570F256C5 --`
7			`-- project by Valerio Venturi ELMA Riva del Garda (TN) Italy (2009) --`
8			`-- Date: 16/10/2009 --`
9			`---------------------------------------------------------------------------------------`
10
11			`library IEEE;`
12			`use IEEE.std_logic_1164.all; -- defines std_logic types`
13
14			`-- global architecture`
15			`entity v65c816_bench is`
16			`end v65c816_bench;`
17
18			`use work.v65c816;`
19
20			`architecture behavior of v65c816_bench is`
21			`component v65c816 is`
22			`port( clk0: in STD_LOGIC; -- PHASE0 clock input`
23			`res: in STD_LOGIC; -- reset input`
24			`irq: in STD_LOGIC; -- interrupt request input`
25			`nmi: in STD_LOGIC; -- not maskable interrupt input`
26			`rdy: in STD_LOGIC; -- wait state input (read/write)`
27			`rw: out STD_LOGIC; -- read/write out`
28			`vpa: out STD_LOGIC; -- vpa`
29			`vda: out STD_LOGIC; -- vda`
30			`vp: out STD_LOGIC; -- vector pull`
31			`ope: out STD_LOGIC; -- microcode end`
32			`e: out STD_LOGIC; -- emulation (1)/native mode (0)`
33			`m: out STD_LOGIC; -- M status`
34			`x: out STD_LOGIC; -- X status`
35			`op_exp: out STD_LOGIC; -- two byte instruction running`
36			`addr: out STD_LOGIC_VECTOR(23 downto 0); -- 16 bit address bus out`
37			`data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus`
38			`data_out: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit output data bus`
39			`a_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register`
40			`x_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register`
41			`y_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register`
42			`s_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register`
43			`op_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register`
44			`p_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register`
45			`k_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register`
46			`b_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register`
47			`o_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register`
48			`mcode: out STD_LOGIC_VECTOR(3 downto 0) -- 4 bit microcode sequence register`
49			`);`
50			`end component;`
51
52			`signal clk0,res,irq,nmi,rdy,rw,vpa,vda,vp,ope,e,m,x,op_exp: STD_LOGIC;`
53			`signal addr: STD_LOGIC_VECTOR(23 downto 0);`
54			`signal data_in: STD_LOGIC_VECTOR(7 downto 0);`
55			`signal data_out: STD_LOGIC_VECTOR(7 downto 0);`
56			`signal a_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register`
57			`signal x_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register`
58			`signal y_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register`
59			`signal s_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register`
60			`signal op_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register`
61			`signal p_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register`
62			`signal k_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register`
63			`signal b_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register`
64			`signal o_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register`
65			`signal mcode: STD_LOGIC_VECTOR(3 downto 0); -- 4 bit microcode sequence register`
66
67			`constant clk_period: time := 50 ns;`
68			`--signal clock: STD_LOGIC := '0';`
69
70			`begin`
71			`u1: v65c816 port map(`
72			`clk0,`
73			`res,`
74			`irq,`
75			`nmi,`
76			`rdy,`
77			`rw,`
78			`vpa,`
79			`vda,`
80			`vp,`
81			`ope,`
82			`e,`
83			`m,`
84			`x,`
85			`op_exp,`
86			`addr,`
87			`data_in,`
88			`data_out,`
89			`a_reg,`
90			`x_reg,`
91			`y_reg,`
92			`s_reg,`
93			`op_reg,`
94			`p_reg,`
95			`k_reg,`
96			`b_reg,`
97			`o_reg,`
98			`mcode`
99			`);`
100
101
102			`tst_clock: process -- 10 MHZ (period 100 ns) clock generation`
103			`variable clktmp: STD_LOGIC := '0';`
104			`begin`
105			`clktmp := not clktmp;`
106			`clk0 <= clktmp;`
107			`wait for 50 ns;`
108			`end process;`
109
110			`stimulus: process`
111			`begin`
112			`-- signal initialization before reset`
113			`res <= '0';`
114			`irq <= '1';`
115			`nmi <= '1';`
116			`rdy <= '1';`
117			`wait for 350 ns;`
118
119			`-- device reset completed`
120			`res <= '1';`
121			`wait for 600 ns;`
122			`data_in <= "00000000"; -- fetch lsb reset PC vector 0x00`
123			`wait for 50 ns;`
124
125			`data_in <= "ZZZZZZZZ";`
126			`wait for 50 ns;`
127			`data_in <= "11000001"; -- fetch msb reset PC vector 0xc1 (0xc100)`
128			`wait for 70 ns;`
129			`data_in <= "ZZZZZZZZ";`
130
131			`wait for 50 ns;`
132			`data_in <= "00011000"; -- CLC`
133			`wait for 50 ns;`
134			`data_in <= "ZZZZZZZZ";`
135
136			`wait for 50 ns;`
137			`data_in <= "11111011"; -- XCE`
138			`wait for 50 ns;`
139			`data_in <= "ZZZZZZZZ";`
140
141			`wait for 50 ns;`
142			`data_in <= "ZZZZZZZZ"; -- XCE execution`
143			`wait for 50 ns;`
144			`data_in <= "ZZZZZZZZ";`
145
146			`wait for 50 ns;`
147			`data_in <= "11000010"; -- REP #%00100000`
148			`wait for 50 ns;`
149			`data_in <= "ZZZZZZZZ";`
150
151			`wait for 50 ns;`
152			`data_in <= "00100000"; -- $20`
153			`wait for 50 ns;`
154			`data_in <= "ZZZZZZZZ";`
155
156			`data_in <= "ZZZZZZZZ";`
157			`wait for 50 ns;`
158			`data_in <= "10101001"; -- LDA #$0000`
159			`wait for 50 ns;`
160			`data_in <= "ZZZZZZZZ";`
161
162			`wait for 50 ns;`
163			`data_in <= "00000000"; -- $00`
164			`wait for 50 ns;`
165			`data_in <= "ZZZZZZZZ";`
166
167			`wait for 50 ns;`
168			`data_in <= "00000000"; -- $00`
169			`wait for 50 ns;`
170			`data_in <= "ZZZZZZZZ";`
171
172			`wait for 50 ns;`
173			`data_in <= "00011000"; -- CLC`
174			`wait for 50 ns;`
175			`data_in <= "ZZZZZZZZ";`
176
177			`data_in <= "ZZZZZZZZ";`
178			`wait for 50 ns;`
179			`data_in <= "01101001"; -- ADC #$0001`
180			`wait for 50 ns;`
181			`data_in <= "ZZZZZZZZ";`
182
183			`data_in <= "ZZZZZZZZ";`
184			`wait for 50 ns;`
185			`data_in <= "00000001"; -- $01`
186			`wait for 50 ns;`
187			`data_in <= "ZZZZZZZZ";`
188
189			`data_in <= "ZZZZZZZZ";`
190			`wait for 50 ns;`
191			`data_in <= "00000000"; -- $00`
192			`wait for 50 ns;`
193			`data_in <= "ZZZZZZZZ";`
194
195			`data_in <= "ZZZZZZZZ";`
196			`wait for 50 ns;`
197			`data_in <= "00111000"; -- SEC`
198			`wait for 50 ns;`
199			`data_in <= "ZZZZZZZZ";`
200
201			`data_in <= "ZZZZZZZZ";`
202			`wait for 50 ns;`
203			`data_in <= "11101001"; -- SBC #0002`
204			`wait for 50 ns;`
205			`data_in <= "ZZZZZZZZ";`
206
207			`data_in <= "ZZZZZZZZ";`
208			`wait for 50 ns;`
209			`data_in <= "00000010"; -- $02`
210			`wait for 50 ns;`
211			`data_in <= "ZZZZZZZZ";`
212
213			`data_in <= "ZZZZZZZZ";`
214			`wait for 50 ns;`
215			`data_in <= "00000000"; -- $00`
216			`wait for 50 ns;`
217			`data_in <= "ZZZZZZZZ";`
218
219			`data_in <= "ZZZZZZZZ";`
220			`wait for 50 ns;`
221			`data_in <= "11101010"; -- NOP`
222			`wait for 50 ns;`
223			`data_in <= "ZZZZZZZZ";`
224
225			`data_in <= "ZZZZZZZZ";`
226			`wait for 50 ns;`
227			`data_in <= "11101010"; -- NOP`
228			`wait for 50 ns;`
229			`data_in <= "ZZZZZZZZ";`
230
231			`data_in <= "ZZZZZZZZ";`
232			`wait for 50 ns;`
233			`data_in <= "11101010"; -- NOP`
234			`wait for 50 ns;`
235			`data_in <= "ZZZZZZZZ";`
236
237			`data_in <= "ZZZZZZZZ";`
238			`wait for 50 ns;`
239			`data_in <= "11101010"; -- NOP`
240			`wait for 50 ns;`
241			`data_in <= "ZZZZZZZZ";`
242
243			`data_in <= "ZZZZZZZZ";`
244			`wait for 50 ns;`
245			`data_in <= "11101010"; -- NOP`
246			`wait for 50 ns;`
247			`data_in <= "ZZZZZZZZ";`
248
249			`data_in <= "ZZZZZZZZ";`
250			`wait for 50 ns;`
251			`data_in <= "11101010"; -- NOP`
252			`wait for 50 ns;`
253			`data_in <= "ZZZZZZZZ";`
254
255
256			`--wait for 1000000 ns;`
257			`wait;`
258			`end process;`
259			`end behavior;`
260
261
262