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tomburkeii |
Verilog Fixed point math library
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Original work by Sam Skalicky, originally found here:
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http://opencores.org/project,fixed_point_arithmetic_parameterized
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Extended, updated, and heavily commented by Tom Burke (tomburkeii@gmail.com)
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This library includes the basic math functions for the Verilog Language,
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for implementation on FPGAs.
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All units have been simulated and synthesized for Xilinx Spartan 3E devices
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using the Xilinx ISE WebPack tools v14.7
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These math routines use a signed magnitude Q,N format, where N is the total
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number of bits used, and Q is the number of fractional bits used. For
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instance, 15,32 would represent a 32-bit number with 15 fractional bits,
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16 integer bits, and 1 sign bit as shown below:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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This library contains the following modules:
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qadd.v - Addition module; adds 2 numbers of any sign.
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qdiv.v - Division module; divides two numbers using a right-shift and
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subtract algorithm - requires an input clock
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qmult.v - Multiplication module; purely combinational for systems that
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will support it
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qmults.v - Multiplication module; uses a left-shift and add algorithm -
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requires an input clock (for systems that cannot support
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the synthesis of a combinational multiplier)
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Test_add.v - Test fixture for the qadd.v module
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Test_mult.v - Test fixture for the qmult.v module
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TestDiv.v - Test fixture for the qdiv.v module
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TestMultS.v - Test fixture for the qmults.v module
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These math routines default to a (Q,N) of (15,32), but are easily customizable
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to your application by changing their input parameters. For instance, an
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unmodified use of (15,32) would look something like this:
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qadd my_adder(
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.a(addend_a),
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.b(addend_b),
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.c(result)
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);
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To change this to an (8,23) notation, for instance, the same module would be
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instantiated thusly:
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qadd #(8,23) my_adder(
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.a(addend_a),
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.b(addend_b),
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.c(result)
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);
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The following is a description of each module
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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qadd.v - A simple combinational addition module.
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sum = addend + addend
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Input format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Inputs:
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a - addend 1
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b - addend 2
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Output format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Output:
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c - result
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NOTE: There is no error detection for an overflow. It is up to the designer
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to ensure that an overflow cannot occur!!
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Example usage:
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qadd #(Q,N) my_adder(
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.a(addend_a),
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.b(addend_b),
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.c(result)
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);
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For subtraction, set the sign bit for the negative number. (subtraction is
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the addition of a negative, right?)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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qmult.v - A simple combinational multiplication module.
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Input format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Inputs:
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i_multiplicand - multiplicand
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i_multiplier - multiplier
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Output format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Output:
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o_result - result
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ovr - overflow flag
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NOTE: This module assumes a system that supports the synthesis of
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combinational multipliers. If your device/synthesizer does not
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support this for your particular application, then use the
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"qmults.v" module.
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NOTE: Notice that the output format is identical to the input format! To
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properly use this module, you need to either ensure that you maximum
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result never exceeds the format, or incorporate the overflow flag
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into your design
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Example usage:
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qmult #(Q,N) my_multiplier(
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.i_multiplicand(multiplicand),
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.i_multiplier(multiplier),
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.o_result(result),
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.ovr(overflow_flag)
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);
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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qmults.v - A multi-clock multiplication module that uses a left-shift
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and add algorithm.
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result = multiplicand x multiplier
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Input format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Inputs:
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i_multiplicand - multiplicand
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i_multiplier - multiplier
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i_start - Start flag; set this bit high ("1") to start the
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operation when the last operation is completed. This
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bit is ignored until o_complete is asserted.
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i_clk - input clock; internal workings occur on the rising edge
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Output format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Output:
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o_result_out - result
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o_complete - computation complete flag; asserted ("1") when the
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operation is completed
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o_overflow - overflow flag; asserted ("1") to indicate that an
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overflow has occurred.
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NOTE: This module is "time deterministic ." - that is, it should always
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take the same number of clock cycles to complete an operation,
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regardless of the inputs (N+1 clocks)
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NOTE: Notice that the output format is identical to the input format! To
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properly use this module, you need to either ensure that you maximum
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result never exceeds the format, or incorporate the overflow flag
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into your design
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Example usage:
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qmults #(Q,N) my_multiplier(
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.i_multiplicand(multiplicand),
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.i_multiplier(multiplier),
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.i_start(start),
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.i_clk(clock),
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.o_result(result),
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.o_complete(done),
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.o_overflow(overflow_flag)
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);
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The qmults.v module begins computation when the start conditions are met:
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o_complete == 1'b1;
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i_start == 1'b1;
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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qdiv.v - A multi-clock division module that uses a right-shift
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and add algorithm.
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quotient = dividend / divisor
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Input format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Inputs:
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i_dividend - dividend
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i_divisor - divisor
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i_start - Start flag; set this bit high ("1") to start the
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operation when the last operation is completed. This
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bit is ignored until o_complete is asserted.
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i_clk - input clock; internal workings occur on the rising edge
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Output format:
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|1|<- N-Q-1 bits ->|<--- Q bits -->|
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|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
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Output:
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o_quotient_out - result
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o_complete - computation complete flag; asserted ("1") when the
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operation is completed
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o_overflow - overflow flag; asserted ("1") to indicate that an
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overflow has occurred.
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NOTE: This module is "time deterministic ." - that is, it should always
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take the same number of clock cycles to complete an operation,
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regardless of the inputs (N+Q+1 clocks)
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NOTE: Notice that the output format is identical to the input format! To
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properly use this module, you need to either ensure that you maximum
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result never exceeds the format, or incorporate the overflow flag
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into your design
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Example usage:
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qdiv #(Q,N) my_divider(
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.i_dividend(dividend),
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.i_divisor(divisor),
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.i_start(start),
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.i_clk(clock),
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.o_quotient_out(result),
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.o_complete(done),
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.o_overflow(overflow_flag)
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);
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The qdiv.v module begins computation when the start conditions are met:
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o_complete == 1'b1;
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i_start == 1'b1;
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Suggestions, Kudos, or Complaints? Feel free to contact me - but remember,
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this stuff is free!
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