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Subversion Repositories versatile_counter

[/] [versatile_counter/] [trunk/] [rtl/] [verilog/] [versatile_counter.v] - Blame information for rev 5

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`include "versatile_counter_defines.v"
`define LFSR_LENGTH `CNT_LENGTH
`include "lfsr_polynom.v"
`let CNT_INDEX=CNT_LENGTH-1
module `CNT_MODULE_NAME
  (
`ifdef CNT_TYPE_GRAY
    output reg [`CNT_LENGTH:1] q,
 `ifdef CNT_Q_BIN
    output [`CNT_LENGTH:1]    q_bin,
 `endif
`else
 `ifdef CNT_Q
    output [`CNT_LENGTH:1]    q,
 `endif
`endif
`ifdef CNT_CLEAR
    input clear,
`endif
`ifdef CNT_SET
    input set,
`endif
`ifdef CNT_REW
    input rew,
`endif
`ifdef CNT_CE
    input cke,
`endif
`ifdef CNT_QNEXT
    output [`CNT_LENGTH:1] q_next,
`endif
`ifdef CNT_Z
    output z,
`endif
`ifdef CNT_ZQ
    output reg zq,
`endif
    input clk,
    input rst
   );
 
`ifdef CNT_SET
 `ifndef CNT_SET_VALUE
  `define CNT_SET_VALUE 0
 `endif
   parameter set_value = `CNT_SET_VALUE;
`endif
`ifdef CNT_WRAP
 `ifndef CNT_WRAP_VALUE
  `define CNT_WRAP_VALUE 0
 `endif
   parameter wrap_value = `CNT_WRAP_VALUE;
`endif
 
   // internal q reg
   reg [`CNT_LENGTH:1] qi;
 
`ifndef CNT_QNEXT
   wire [`CNT_LENGTH:1] q_next;
`endif
`ifdef CNT_REW
   wire [`CNT_LENGTH:1] q_next_fw;
   wire [`CNT_LENGTH:1] q_next_rew;
`endif
 
`ifndef CNT_REW
   assign q_next =
`else
     assign q_next_fw =
`endif
`ifdef CNT_CLEAR
       clear ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_SET
         set ? set_value :
`endif
`ifdef CNT_WRAP
           (qi == wrap_value) ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_TYPE_LFSR
             {qi[`CNT_INDEX:1],~(`LFSR_FB)};
`else
   qi + `CNT_LENGTH'd1;
`endif
 
`ifdef CNT_REW
   assign q_next_rew =
 `ifdef CNT_CLEAR
     clear ? `CNT_LENGTH'd0 :
 `endif
 `ifdef CNT_SET
       set ? set_value :
 `endif
 `ifdef CNT_WRAP
         (qi == `CNT_LENGTH'd0) ? wrap_value :
 `endif
 `ifdef CNT_TYPE_LFSR
           {~(`LFSR_FB_REW),qi[`CNT_LENGTH:2]};
 `else
   qi - `CNT_LENGTH'd1;
 `endif
`endif
 
`ifdef CNT_REW
   assign q_next = rew ? q_next_rew : q_next_fw;
`endif
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= `CNT_LENGTH'd0;
     else
`ifdef CNT_CE
   if (cke)
`endif
     qi <= q_next;
 
`ifdef CNT_Q
 `ifdef CNT_TYPE_GRAY
   always @ (posedge clk or posedge rst)
     if (rst)
       q <= `CNT_LENGTH'd0;
     else
  `ifdef CNT_CE
       if (cke)
  `endif
         q <= (q_next>>1) ^ q_next;
  `ifdef CNT_Q_BIN
   assign q_bin = qi;
  `endif
 `else
   assign q = q_next;
 `endif
`endif
 
`ifdef CNT_Z
   assign z = (q == `CNT_LENGTH'd0);
`endif
 
`ifdef CNT_ZQ
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b0;
     else
 `ifdef CNT_CE
       if (cke)
 `endif
         zq <= q_next == `CNT_LENGTH'd0;
`endif
endmodule

Line No.	Rev	Author	Line
1	2	unneback	`include "versatile_counter_defines.v"
2			`define LFSR_LENGTH `CNT_LENGTH
3			`include "lfsr_polynom.v"
4			`let CNT_INDEX=CNT_LENGTH-1
5			module `CNT_MODULE_NAME
6			`(`
7			`ifdef CNT_TYPE_GRAY
8	5	unneback	output reg [`CNT_LENGTH:1] q,
9	4	unneback	`ifdef CNT_Q_BIN
10			output [`CNT_LENGTH:1] q_bin,
11			`endif
12	2	unneback	`else
13			`ifdef CNT_Q
14			output [`CNT_LENGTH:1] q,
15			`endif
16			`endif
17			`ifdef CNT_CLEAR
18			`input clear,`
19			`endif
20			`ifdef CNT_SET
21			`input set,`
22			`endif
23			`ifdef CNT_REW
24			`input rew,`
25			`endif
26			`ifdef CNT_CE
27			`input cke,`
28			`endif
29			`ifdef CNT_QNEXT
30			output [`CNT_LENGTH:1] q_next,
31			`endif
32			`ifdef CNT_Z
33			`output z,`
34			`endif
35			`ifdef CNT_ZQ
36			`output reg zq,`
37			`endif
38			`input clk,`
39			`input rst`
40			`);`
41
42			`ifdef CNT_SET
43	5	unneback	`ifndef CNT_SET_VALUE
44			`define CNT_SET_VALUE 0
45			`endif
46	2	unneback	parameter set_value = `CNT_SET_VALUE;
47			`endif
48			`ifdef CNT_WRAP
49	5	unneback	`ifndef CNT_WRAP_VALUE
50			`define CNT_WRAP_VALUE 0
51			`endif
52	2	unneback	parameter wrap_value = `CNT_WRAP_VALUE;
53			`endif
54
55			`// internal q reg`
56			reg [`CNT_LENGTH:1] qi;
57
58			`ifndef CNT_QNEXT
59			wire [`CNT_LENGTH:1] q_next;
60			`endif
61			`ifdef CNT_REW
62			wire [`CNT_LENGTH:1] q_next_fw;
63			wire [`CNT_LENGTH:1] q_next_rew;
64			`endif
65
66			`ifndef CNT_REW
67			`assign q_next =`
68			`else
69			`assign q_next_fw =`
70			`endif
71			`ifdef CNT_CLEAR
72			clear ? `CNT_LENGTH'd0 :
73			`endif
74			`ifdef CNT_SET
75			`set ? set_value :`
76			`endif
77			`ifdef CNT_WRAP
78			(qi == wrap_value) ? `CNT_LENGTH'd0 :
79			`endif
80			`ifdef CNT_TYPE_LFSR
81			{qi[`CNT_INDEX:1],~(`LFSR_FB)};
82			`else
83			qi + `CNT_LENGTH'd1;
84			`endif
85
86			`ifdef CNT_REW
87			`assign q_next_rew =`
88			`ifdef CNT_CLEAR
89			clear ? `CNT_LENGTH'd0 :
90			`endif
91			`ifdef CNT_SET
92			`set ? set_value :`
93			`endif
94			`ifdef CNT_WRAP
95			(qi == `CNT_LENGTH'd0) ? wrap_value :
96			`endif
97			`ifdef CNT_TYPE_LFSR
98			{~(`LFSR_FB_REW),qi[`CNT_LENGTH:2]};
99			`else
100			qi - `CNT_LENGTH'd1;
101			`endif
102			`endif
103
104			`ifdef CNT_REW
105			`assign q_next = rew ? q_next_rew : q_next_fw;`
106			`endif
107
108			`always @ (posedge clk or posedge rst)`
109			`if (rst)`
110			qi <= `CNT_LENGTH'd0;
111			`else`
112			`ifdef CNT_CE
113			`if (cke)`
114			`endif
115			`qi <= q_next;`
116
117			`ifdef CNT_Q
118			`ifdef CNT_TYPE_GRAY
119			`always @ (posedge clk or posedge rst)`
120			`if (rst)`
121			q <= `CNT_LENGTH'd0;
122			`else`
123			`ifdef CNT_CE
124			`if (cke)`
125			`endif
126			`q <= (q_next>>1) ^ q_next;`
127	4	unneback	`ifdef CNT_Q_BIN
128			`assign q_bin = qi;`
129			`endif
130	2	unneback	`else
131			`assign q = q_next;`
132			`endif
133			`endif
134
135			`ifdef CNT_Z
136			assign z = (q == `CNT_LENGTH'd0);
137			`endif
138
139			`ifdef CNT_ZQ
140			`always @ (posedge clk or posedge rst)`
141			`if (rst)`
142			`zq <= 1'b0;`
143			`else`
144			`ifdef CNT_CE
145			`if (cke)`
146			`endif
147			zq <= q_next == `CNT_LENGTH'd0;
148			`endif
149			`endmodule`

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[/] [versatile_counter/] [trunk/] [rtl/] [verilog/] [versatile_counter.v] - Blame information for rev 5