URL https://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk

Subversion Repositories versatile_counter

[/] [versatile_counter/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim.do] - Blame information for rev 36

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vlib work
 
vlog ../../../rtl/verilog/vc.v
vlog ../../../bench/versatile_counter_tb.v
 
vsim -voptargs=+acc work.lfsr_tb
 
do ../bin/wave.do
 
run 10 us
 

Line No.	Rev	Author	Line
1	2	unneback	`vlib work`
2
3	25	unneback	`vlog ../../../rtl/verilog/vc.v`
4	2	unneback	`vlog ../../../bench/versatile_counter_tb.v`
5
6			`vsim -voptargs=+acc work.lfsr_tb`
7
8			`do ../bin/wave.do`
9
10			`run 10 us`
11

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Subversion Repositories versatile_counter

[/] [versatile_counter/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim.do] - Blame information for rev 36