1 |
19 |
unneback |
// megafunction wizard: %LPM_FF%
|
2 |
|
|
// GENERATION: STANDARD
|
3 |
|
|
// VERSION: WM1.0
|
4 |
|
|
// MODULE: lpm_ff
|
5 |
|
|
|
6 |
|
|
// ============================================================
|
7 |
|
|
// File Name: dff_sr.v
|
8 |
|
|
// Megafunction Name(s):
|
9 |
|
|
// lpm_ff
|
10 |
|
|
//
|
11 |
|
|
// Simulation Library Files(s):
|
12 |
|
|
// lpm
|
13 |
|
|
// ============================================================
|
14 |
|
|
// ************************************************************
|
15 |
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
16 |
|
|
//
|
17 |
|
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
18 |
|
|
// ************************************************************
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
//Copyright (C) 1991-2010 Altera Corporation
|
22 |
|
|
//Your use of Altera Corporation's design tools, logic functions
|
23 |
|
|
//and other software and tools, and its AMPP partner logic
|
24 |
|
|
//functions, and any output files from any of the foregoing
|
25 |
|
|
//(including device programming or simulation files), and any
|
26 |
|
|
//associated documentation or information are expressly subject
|
27 |
|
|
//to the terms and conditions of the Altera Program License
|
28 |
|
|
//Subscription Agreement, Altera MegaCore Function License
|
29 |
|
|
//Agreement, or other applicable license agreement, including,
|
30 |
|
|
//without limitation, that your use is for the sole purpose of
|
31 |
|
|
//programming logic devices manufactured by Altera and sold by
|
32 |
|
|
//Altera or its authorized distributors. Please refer to the
|
33 |
|
|
//applicable agreement for further details.
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
// synopsys translate_off
|
37 |
|
|
`timescale 1 ps / 1 ps
|
38 |
|
|
// synopsys translate_on
|
39 |
|
|
module dff_sr (
|
40 |
|
|
aclr,
|
41 |
|
|
aset,
|
42 |
|
|
clock,
|
43 |
|
|
data,
|
44 |
|
|
q);
|
45 |
|
|
|
46 |
|
|
input aclr;
|
47 |
|
|
input aset;
|
48 |
|
|
input clock;
|
49 |
|
|
input data;
|
50 |
|
|
output q;
|
51 |
|
|
|
52 |
|
|
wire [0:0] sub_wire0;
|
53 |
|
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
54 |
|
|
wire q = sub_wire1;
|
55 |
|
|
wire sub_wire2 = data;
|
56 |
|
|
wire sub_wire3 = sub_wire2;
|
57 |
|
|
|
58 |
|
|
lpm_ff lpm_ff_component (
|
59 |
|
|
.aclr (aclr),
|
60 |
|
|
.clock (clock),
|
61 |
|
|
.data (sub_wire3),
|
62 |
|
|
.aset (aset),
|
63 |
|
|
.q (sub_wire0)
|
64 |
|
|
// synopsys translate_off
|
65 |
|
|
,
|
66 |
|
|
.aload (),
|
67 |
|
|
.enable (),
|
68 |
|
|
.sclr (),
|
69 |
|
|
.sload (),
|
70 |
|
|
.sset ()
|
71 |
|
|
// synopsys translate_on
|
72 |
|
|
);
|
73 |
|
|
defparam
|
74 |
|
|
lpm_ff_component.lpm_fftype = "DFF",
|
75 |
|
|
lpm_ff_component.lpm_type = "LPM_FF",
|
76 |
|
|
lpm_ff_component.lpm_width = 1;
|
77 |
|
|
|
78 |
|
|
|
79 |
|
|
endmodule
|
80 |
|
|
|
81 |
|
|
// ============================================================
|
82 |
|
|
// CNX file retrieval info
|
83 |
|
|
// ============================================================
|
84 |
|
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
85 |
|
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
86 |
|
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
87 |
|
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
88 |
|
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
89 |
|
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
90 |
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
91 |
|
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
92 |
|
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
93 |
|
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
94 |
|
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
95 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
96 |
|
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
97 |
|
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
98 |
|
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
99 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
100 |
|
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
101 |
|
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
102 |
|
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
103 |
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
104 |
|
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
105 |
|
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
106 |
|
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
107 |
|
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
108 |
|
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
109 |
|
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
110 |
|
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
111 |
|
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
112 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
113 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
114 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
115 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
116 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
117 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
118 |
|
|
// Retrieval info: LIB_FILE: lpm
|