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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [gray_counter_defines.v] - Blame information for rev 17

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// module name
`define CNT_MODULE_NAME gray_counter
 
// counter type = [BINARY, GRAY, LFSR]
//`define CNT_TYPE_BINARY
`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
`define CNT_Q
 
// number of CNT bins
`define CNT_LENGTH 6
 
// clear
//`define CNT_CLEAR
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h9
 
// wrap around creates shorter cycle than maximum length
//`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'h9
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
//`define CNT_ZQ
 

Line No.	Rev	Author	Line
1	15	unneback	`// module name`
2			`define CNT_MODULE_NAME gray_counter
3
4			`// counter type = [BINARY, GRAY, LFSR]`
5			//`define CNT_TYPE_BINARY
6			`define CNT_TYPE_GRAY
7			//`define CNT_TYPE_LFSR
8
9			`// q as output`
10			`define CNT_Q
11
12			`// number of CNT bins`
13			`define CNT_LENGTH 6
14
15			`// clear`
16			//`define CNT_CLEAR
17
18			`// set`
19			//`define CNT_SET
20			`define CNT_SET_VALUE `CNT_LENGTH'h9
21
22			`// wrap around creates shorter cycle than maximum length`
23			//`define CNT_WRAP
24			`define CNT_WRAP_VALUE `CNT_LENGTH'h9
25
26			`// clock enable`
27			`define CNT_CE
28
29			`// q_next as an output`
30			//`define CNT_QNEXT
31
32			`// q=0 as an output`
33			//`define CNT_Z
34
35			`// q_next=0 as a registered output`
36			//`define CNT_ZQ
37

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [gray_counter_defines.v] - Blame information for rev 17