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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [sd_counter_defines.v] - Blame information for rev 9

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// module name
`define CNT_MODULE_NAME sd_counter
 
// counter type = [BINARY, GRAY, LFSR]
//`define CNT_TYPE_BINARY
`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
`define CNT_Q
// for gray type counter optional binary output
`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 9
 
// clear
//`define CNT_CLEAR
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h9
 
// wrap around creates shorter cycle than maximum length
//`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'h9
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
//`define CNT_ZQ
 

Line No.	Rev	Author	Line
1	7	unneback	`// module name`
2			`define CNT_MODULE_NAME sd_counter
3
4			`// counter type = [BINARY, GRAY, LFSR]`
5			//`define CNT_TYPE_BINARY
6			`define CNT_TYPE_GRAY
7			//`define CNT_TYPE_LFSR
8
9			`// q as output`
10			`define CNT_Q
11			`// for gray type counter optional binary output`
12			`define CNT_Q_BIN
13
14			`// number of CNT bins`
15			`define CNT_LENGTH 9
16
17			`// clear`
18			//`define CNT_CLEAR
19
20			`// set`
21			//`define CNT_SET
22			`define CNT_SET_VALUE `CNT_LENGTH'h9
23
24			`// wrap around creates shorter cycle than maximum length`
25			//`define CNT_WRAP
26			`define CNT_WRAP_VALUE `CNT_LENGTH'h9
27
28			`// clock enable`
29			`define CNT_CE
30
31			`// q_next as an output`
32			//`define CNT_QNEXT
33
34			`// q=0 as an output`
35			//`define CNT_Z
36
37			`// q_next=0 as a registered output`
38			//`define CNT_ZQ
39

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [sd_counter_defines.v] - Blame information for rev 9