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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Blame information for rev 26

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// true dual port RAM, sync
 
`ifdef ACTEL
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`endif
module vfifo_dual_port_ram_`TYPE
  (
   // A side
   d_a,
`ifdef DW
   q_a,
`endif
   adr_a,
   we_a,
`ifdef DC
   clk_a,
`endif
   // B side
   q_b,
   adr_b,
`ifdef DW
   d_b,
   we_b,
`endif
`ifdef DC
   clk_b
`else
   clk
`endif
   );
 
   parameter DATA_WIDTH = 32;
   parameter ADDR_WIDTH = 8;
 
   input [(DATA_WIDTH-1):0]      d_a;
   input [(ADDR_WIDTH-1):0]       adr_a;
   input [(ADDR_WIDTH-1):0]       adr_b;
   input                         we_a;
   output [(DATA_WIDTH-1):0]      q_b;
`ifdef DW
   input [(DATA_WIDTH-1):0]       d_b;
   output reg [(DATA_WIDTH-1):0] q_a;
   input                         we_b;
`endif
`ifdef DC
   input                         clk_a, clk_b;
`else
   input                         clk;
`endif
 
`ifndef DW
   reg [(ADDR_WIDTH-1):0]         adr_b_reg;
`else
   reg [(DATA_WIDTH-1):0]         q_b;
`endif
 
   // Declare the RAM variable
   reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
 
`ifdef DC
   always @ (posedge clk_a)
`else
   always @ (posedge clk)
`endif
`ifdef DW
     begin // Port A
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
`else
   if (we_a)
     ram[adr_a] <= d_a;
`endif
 
`ifdef DC
   always @ (posedge clk_b)
`else
   always @ (posedge clk)
`endif
`ifdef DW
     begin // Port b
          q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
`else // !`ifdef DW
   adr_b_reg <= adr_b;
 
   assign q_b = ram[adr_b_reg];
`endif // !`ifdef DW
 
endmodule // true_dual_port_ram_sync

Line No.	Rev	Author	Line
1	2	unneback	`// true dual port RAM, sync`
2	26	unneback
3			`ifdef ACTEL
4			`define SYN /synthesis syn_ramstyle = "no_rw_check"/
5			`endif
6	12	unneback	module vfifo_dual_port_ram_`TYPE
7	2	unneback	`(`
8			`// A side`
9			`d_a,`
10			`ifdef DW
11			`q_a,`
12			`endif
13			`adr_a,`
14			`we_a,`
15			`ifdef DC
16			`clk_a,`
17			`endif
18			`// B side`
19	4	unneback	`q_b,`
20	2	unneback	`adr_b,`
21			`ifdef DW
22			`d_b,`
23			`we_b,`
24			`endif
25			`ifdef DC
26			`clk_b`
27			`else
28			`clk`
29			`endif
30			`);`
31
32	18	unneback	`parameter DATA_WIDTH = 32;`
33			`parameter ADDR_WIDTH = 8;`
34	2	unneback
35	4	unneback	`input [(DATA_WIDTH-1):0] d_a;`
36			`input [(ADDR_WIDTH-1):0] adr_a;`
37			`input [(ADDR_WIDTH-1):0] adr_b;`
38	2	unneback	`input we_a;`
39	4	unneback	`output [(DATA_WIDTH-1):0] q_b;`
40	2	unneback	`ifdef DW
41	4	unneback	`input [(DATA_WIDTH-1):0] d_b;`
42	2	unneback	`output reg [(DATA_WIDTH-1):0] q_a;`
43			`input we_b;`
44			`endif
45			`ifdef DC
46			`input clk_a, clk_b;`
47			`else
48			`input clk;`
49			`endif
50	4	unneback
51			`ifndef DW
52			`reg [(ADDR_WIDTH-1):0] adr_b_reg;`
53			`else
54			`reg [(DATA_WIDTH-1):0] q_b;`
55			`endif
56	2	unneback
57			`// Declare the RAM variable`
58	26	unneback	reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
59	2	unneback
60			`ifdef DC
61			`always @ (posedge clk_a)`
62			`else
63			`always @ (posedge clk)`
64			`endif
65			`ifdef DW
66			`begin // Port A`
67	15	unneback	`q_a <= ram[adr_a];`
68	2	unneback	`if (we_a)`
69	4	unneback	`ram[adr_a] <= d_a;`
70	2	unneback	`end`
71			`else
72			`if (we_a)`
73	4	unneback	`ram[adr_a] <= d_a;`
74	2	unneback	`endif
75
76			`ifdef DC
77	4	unneback	`always @ (posedge clk_b)`
78	2	unneback	`else
79			`always @ (posedge clk)`
80			`endif
81			`ifdef DW
82			`begin // Port b`
83	15	unneback	`q_b <= ram[adr_b];`
84	2	unneback	`if (we_b)`
85	15	unneback	`ram[adr_b] <= d_b;`
86	2	unneback	`end`
87			`else // !`ifdef DW
88	4	unneback	`adr_b_reg <= adr_b;`
89
90			`assign q_b = ram[adr_b_reg];`
91	2	unneback	`endif // !`ifdef DW
92
93			`endmodule // true_dual_port_ram_sync`

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Blame information for rev 26