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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Blame information for rev 2

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1 2 unneback 
// true dual port RAM, sync
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module versatile_fifo_dual_port_ram_dc_2w
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  (
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   // A side
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   d_a,
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`ifdef DW
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   q_a,
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`endif
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   adr_a,
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   we_a,
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`ifdef DC
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   clk_a,
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`endif
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   // B side
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   q_b
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   adr_b,
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`ifdef DW
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   d_b,
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   we_b,
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`endif
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`ifdef DC
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   clk_b
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`else
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   clk
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`endif
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   );
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   parameter DATA_WIDTH = 8;
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   parameter ADDR_WIDTH = 9;
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   input [(DATA_WIDTH-1):0]      data_a;
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   input [(ADDR_WIDTH-1):0]       addr_a;
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   input [(ADDR_WIDTH-1):0]       addr_b;
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   input                         we_a;
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   output reg [(DATA_WIDTH-1):0] q_b;
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`ifdef DW
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   input [(DATA_WIDTH-1):0]       data_b;
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   output reg [(DATA_WIDTH-1):0] q_a;
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   input                         we_b;
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`endif
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`ifdef DC
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   input                         clk_a, clk_b;
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`else
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   input                         clk;
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`endif
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   // Declare the RAM variable
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   reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`ifdef DC
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   always @ (posedge clk_a)
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`else
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   always @ (posedge clk)
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`endif
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`ifdef DW
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     begin // Port A
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        if (we_a)
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          begin
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             ram[addr_a] <= data_a;
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             q_a <= data_a;
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          end
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        else
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          q_a <= ram[addr_a];
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     end
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`else
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   if (we_a)
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     ram[addr_a] <= data_a;
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`endif
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`ifdef DC
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   always @ (posedge clk_a)
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`else
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   always @ (posedge clk)
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`endif
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`ifdef DW
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     begin // Port b
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        if (we_b)
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          begin
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             ram[addr_b] <= data_b;
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             q_b <= data_b;
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          end
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        else
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          q_b <= ram[addr_b];
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     end
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`else // !`ifdef DW
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   q_b <= ram[addr_b];
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`endif // !`ifdef DW
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endmodule // true_dual_port_ram_sync

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