URL https://opencores.org/ocsvn/versatile_io/versatile_io/trunk

Subversion Repositories versatile_io

[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Blame information for rev 14

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//=tab Main
//=comment <b>Versatile IO</b>
//=tab UART
`define UART0
`define UART0_BASE_ADR 32'h90000000
`define UART0_MEM_MAP_HI 31
`define UART0_MEM_MAP_LO 24
`ifdef UART0
`define UART
`endif
//=comment
//`define UART1
`define UART1_BASE 32'h92100000
`define UART1_MEM_MAP_HI 31
`define UART1_MEM_MAP_LO 24
`ifdef UART1
`ifndef UART
`define UART
`endif
`endif

Line No.	Rev	Author	Line
1	2	unneback	`//=tab Main`
2			`//=comment <b>Versatile IO</b>`
3			`//=tab UART`
4			`define UART0
5	14	unneback	`define UART0_BASE_ADR 32'h90000000
6	2	unneback	`define UART0_MEM_MAP_HI 31
7			`define UART0_MEM_MAP_LO 24
8	6	unneback	`ifdef UART0
9			`define UART
10			`endif
11	2	unneback	`//=comment`
12			//`define UART1
13			`define UART1_BASE 32'h92100000
14			`define UART1_MEM_MAP_HI 31
15			`define UART1_MEM_MAP_LO 24
16	6	unneback	`ifdef UART1
17			`ifndef UART
18			`define UART
19			`endif
20			`endif

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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Blame information for rev 14