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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io.v] - Blame information for rev 12

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1 7 unneback
`ifdef UART
2
 module raminfr
3
        (clk, we, a, dpra, di, dpo);
4
parameter addr_width = 4;
5
parameter data_width = 8;
6
parameter depth = 16;
7
input clk;
8
input we;
9
input  [addr_width-1:0] a;
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input  [addr_width-1:0] dpra;
11
input  [data_width-1:0] di;
12
output [data_width-1:0] dpo;
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reg    [data_width-1:0] ram [depth-1:0];
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wire [data_width-1:0] dpo;
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wire  [data_width-1:0] di;
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wire  [addr_width-1:0] a;
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wire  [addr_width-1:0] dpra;
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  always @(posedge clk) begin
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    if (we)
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      ram[a] <= di;
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  end
22
  assign dpo = ram[dpra];
23
endmodule
24
`timescale 1ns/10ps
25
module uart_debug_if (
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wb_dat32_o,
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wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
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lsr, rf_count, tf_count, tstate, rstate
29
) ;
30
input [3-1:0]            wb_adr_i;
31
output [31:0]                                                    wb_dat32_o;
32
input [3:0]                                                      ier;
33
input [3:0]                                                      iir;
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input [1:0]                                                      fcr;
35
input [4:0]                                                      mcr;
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input [7:0]                                                      lcr;
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input [7:0]                                                      msr;
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input [7:0]                                                      lsr;
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input [5-1:0] rf_count;
40
input [5-1:0] tf_count;
41
input [2:0]                                                      tstate;
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input [3:0]                                                      rstate;
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wire [3-1:0]             wb_adr_i;
44
reg [31:0]                                                               wb_dat32_o;
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always @(fcr or ier or iir or lcr or lsr or mcr or msr
46
                        or rf_count or rstate or tf_count or tstate or wb_adr_i)
47
        case (wb_adr_i)
48
                5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
49
                5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
50
                default: wb_dat32_o = 0;
51
        endcase
52
endmodule
53
`timescale 1ns/10ps
54
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
56
input                           clk;
57
input                           wb_rst_i;
58
input   [7:0]    lcr;
59
input                           rf_pop;
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input                           srx_pad_i;
61
input                           enable;
62
input                           rx_reset;
63
input       lsr_mask;
64
output  [9:0]                    counter_t;
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output  [5-1:0]  rf_count;
66
output  [11-1:0] rf_data_out;
67
output                          rf_overrun;
68
output                          rf_error_bit;
69
output [3:0]             rstate;
70
output                          rf_push_pulse;
71
reg     [3:0]    rstate;
72
reg     [3:0]    rcounter16;
73
reg     [2:0]    rbit_counter;
74
reg     [7:0]    rshift;
75
reg             rparity;
76
reg             rparity_error;
77
reg             rframing_error;
78
reg             rbit_in;
79
reg             rparity_xor;
80
reg     [7:0]    counter_b;
81
reg   rf_push_q;
82
reg     [11-1:0] rf_data_in;
83
wire    [11-1:0] rf_data_out;
84
wire      rf_push_pulse;
85
reg                             rf_push;
86
wire                            rf_pop;
87
wire                            rf_overrun;
88
wire    [5-1:0]  rf_count;
89
wire                            rf_error_bit;
90
wire                            break_error = (counter_b == 0);
91
uart_rfifo #(11) fifo_rx(
92
        .clk(           clk             ),
93
        .wb_rst_i(      wb_rst_i        ),
94
        .data_in(       rf_data_in      ),
95
        .data_out(      rf_data_out     ),
96
        .push(          rf_push_pulse           ),
97
        .pop(           rf_pop          ),
98
        .overrun(       rf_overrun      ),
99
        .count(         rf_count        ),
100
        .error_bit(     rf_error_bit    ),
101
        .fifo_reset(    rx_reset        ),
102
        .reset_status(lsr_mask)
103
);
104
wire            rcounter16_eq_7 = (rcounter16 == 4'd7);
105
wire            rcounter16_eq_0 = (rcounter16 == 4'd0);
106
wire            rcounter16_eq_1 = (rcounter16 == 4'd1);
107
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
108
parameter  sr_idle                                      = 4'd0;
109
parameter  sr_rec_start                         = 4'd1;
110
parameter  sr_rec_bit                           = 4'd2;
111
parameter  sr_rec_parity                        = 4'd3;
112
parameter  sr_rec_stop                          = 4'd4;
113
parameter  sr_check_parity              = 4'd5;
114
parameter  sr_rec_prepare                       = 4'd6;
115
parameter  sr_end_bit                           = 4'd7;
116
parameter  sr_ca_lc_parity            = 4'd8;
117
parameter  sr_wait1                                     = 4'd9;
118
parameter  sr_push                                      = 4'd10;
119
always @(posedge clk or posedge wb_rst_i)
120
begin
121
  if (wb_rst_i)
122
  begin
123
     rstate                     <= #1 sr_idle;
124
          rbit_in                               <= #1 1'b0;
125
          rcounter16                    <= #1 0;
126
          rbit_counter          <= #1 0;
127
          rparity_xor           <= #1 1'b0;
128
          rframing_error        <= #1 1'b0;
129
          rparity_error                 <= #1 1'b0;
130
          rparity                               <= #1 1'b0;
131
          rshift                                <= #1 0;
132
          rf_push                               <= #1 1'b0;
133
          rf_data_in                    <= #1 0;
134
  end
135
  else
136
  if (enable)
137
  begin
138
        case (rstate)
139
        sr_idle : begin
140
                        rf_push                           <= #1 1'b0;
141
                        rf_data_in        <= #1 0;
142
                        rcounter16        <= #1 4'b1110;
143
                        if (srx_pad_i==1'b0 & ~break_error)
144
                        begin
145
                                rstate            <= #1 sr_rec_start;
146
                        end
147
                end
148
        sr_rec_start :  begin
149
                        rf_push                           <= #1 1'b0;
150
                                if (rcounter16_eq_7)
151
                                        if (srx_pad_i==1'b1)
152
                                                rstate <= #1 sr_idle;
153
                                        else
154
                                                rstate <= #1 sr_rec_prepare;
155
                                rcounter16 <= #1 rcounter16_minus_1;
156
                        end
157
        sr_rec_prepare:begin
158
                                case (lcr[1:0])
159
                                2'b00 : rbit_counter <= #1 3'b100;
160
                                2'b01 : rbit_counter <= #1 3'b101;
161
                                2'b10 : rbit_counter <= #1 3'b110;
162
                                2'b11 : rbit_counter <= #1 3'b111;
163
                                endcase
164
                                if (rcounter16_eq_0)
165
                                begin
166
                                        rstate          <= #1 sr_rec_bit;
167
                                        rcounter16      <= #1 4'b1110;
168
                                        rshift          <= #1 0;
169
                                end
170
                                else
171
                                        rstate <= #1 sr_rec_prepare;
172
                                rcounter16 <= #1 rcounter16_minus_1;
173
                        end
174
        sr_rec_bit :    begin
175
                                if (rcounter16_eq_0)
176
                                        rstate <= #1 sr_end_bit;
177
                                if (rcounter16_eq_7)
178
                                        case (lcr[1:0])
179
                                        2'b00 : rshift[4:0]  <= #1 {srx_pad_i, rshift[4:1]};
180
                                        2'b01 : rshift[5:0]  <= #1 {srx_pad_i, rshift[5:1]};
181
                                        2'b10 : rshift[6:0]  <= #1 {srx_pad_i, rshift[6:1]};
182
                                        2'b11 : rshift[7:0]  <= #1 {srx_pad_i, rshift[7:1]};
183
                                        endcase
184
                                rcounter16 <= #1 rcounter16_minus_1;
185
                        end
186
        sr_end_bit :   begin
187
                                if (rbit_counter==3'b0)
188
                                        if (lcr[3])
189
                                                rstate <= #1 sr_rec_parity;
190
                                        else
191
                                        begin
192
                                                rstate <= #1 sr_rec_stop;
193
                                                rparity_error <= #1 1'b0;
194
                                        end
195
                                else
196
                                begin
197
                                        rstate <= #1 sr_rec_bit;
198
                                        rbit_counter <= #1 rbit_counter - 1'b1;
199
                                end
200
                                rcounter16 <= #1 4'b1110;
201
                        end
202
        sr_rec_parity: begin
203
                                if (rcounter16_eq_7)
204
                                begin
205
                                        rparity <= #1 srx_pad_i;
206
                                        rstate <= #1 sr_ca_lc_parity;
207
                                end
208
                                rcounter16 <= #1 rcounter16_minus_1;
209
                        end
210
        sr_ca_lc_parity : begin
211
                                rcounter16  <= #1 rcounter16_minus_1;
212
                                rparity_xor <= #1 ^{rshift,rparity};
213
                                rstate      <= #1 sr_check_parity;
214
                          end
215
        sr_check_parity: begin
216
                                case ({lcr[4],lcr[5]})
217
                                        2'b00: rparity_error <= #1  rparity_xor == 0;
218
                                        2'b01: rparity_error <= #1 ~rparity;
219
                                        2'b10: rparity_error <= #1  rparity_xor == 1;
220
                                        2'b11: rparity_error <= #1  rparity;
221
                                endcase
222
                                rcounter16 <= #1 rcounter16_minus_1;
223
                                rstate <= #1 sr_wait1;
224
                          end
225
        sr_wait1 :      if (rcounter16_eq_0)
226
                        begin
227
                                rstate <= #1 sr_rec_stop;
228
                                rcounter16 <= #1 4'b1110;
229
                        end
230
                        else
231
                                rcounter16 <= #1 rcounter16_minus_1;
232
        sr_rec_stop :   begin
233
                                if (rcounter16_eq_7)
234
                                begin
235
                                        rframing_error <= #1 !srx_pad_i;
236
                                        rstate <= #1 sr_push;
237
                                end
238
                                rcounter16 <= #1 rcounter16_minus_1;
239
                        end
240
        sr_push :       begin
241
        if(srx_pad_i | break_error)
242
          begin
243
            if(break_error)
244
                          rf_data_in    <= #1 {8'b0, 3'b100};
245
            else
246
                                rf_data_in  <= #1 {rshift, 1'b0, rparity_error, rframing_error};
247
                  rf_push                 <= #1 1'b1;
248
                                rstate        <= #1 sr_idle;
249
          end
250
        else if(~rframing_error)
251
          begin
252
                        rf_data_in  <= #1 {rshift, 1'b0, rparity_error, rframing_error};
253
                  rf_push                 <= #1 1'b1;
254
                        rcounter16        <= #1 4'b1110;
255
                                rstate            <= #1 sr_rec_start;
256
          end
257
                        end
258
        default : rstate <= #1 sr_idle;
259
        endcase
260
  end
261
end
262
always @ (posedge clk or posedge wb_rst_i)
263
begin
264
  if(wb_rst_i)
265
    rf_push_q <= 0;
266
  else
267
    rf_push_q <= #1 rf_push;
268
end
269
assign rf_push_pulse = rf_push & ~rf_push_q;
270
reg     [9:0]    toc_value;
271
always @(lcr)
272
        case (lcr[3:0])
273
                4'b0000                                                                         : toc_value = 447;
274
                4'b0100                                                                         : toc_value = 479;
275
                4'b0001,        4'b1000                                                 : toc_value = 511;
276
                4'b1100                                                                         : toc_value = 543;
277
                4'b0010, 4'b0101, 4'b1001                               : toc_value = 575;
278
                4'b0011, 4'b0110, 4'b1010, 4'b1101      : toc_value = 639;
279
                4'b0111, 4'b1011, 4'b1110                               : toc_value = 703;
280
                4'b1111                                                                         : toc_value = 767;
281
        endcase
282
wire [7:0]       brc_value;
283
assign          brc_value = toc_value[9:2];
284
always @(posedge clk or posedge wb_rst_i)
285
begin
286
        if (wb_rst_i)
287
                counter_b <= #1 8'd159;
288
        else
289
        if (srx_pad_i)
290
                counter_b <= #1 brc_value;
291
        else
292
        if(enable & counter_b != 8'b0)
293
                counter_b <= #1 counter_b - 1;
294
end
295
reg     [9:0]    counter_t;
296
always @(posedge clk or posedge wb_rst_i)
297
begin
298
        if (wb_rst_i)
299
                counter_t <= #1 10'd639;
300
        else
301
                if(rf_push_pulse || rf_pop || rf_count == 0)
302
                        counter_t <= #1 toc_value;
303
                else
304
                if (enable && counter_t != 10'b0)
305
                        counter_t <= #1 counter_t - 1;
306
end
307
endmodule
308
`timescale 1ns/10ps
309
module uart_regs (clk,
310
        wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
311
        modem_inputs,
312
        stx_pad_o, srx_pad_i,
313
        rts_pad_o, dtr_pad_o, int_o
314
        );
315
input                                                                   clk;
316
input                                                                   wb_rst_i;
317
input [3-1:0]            wb_addr_i;
318
input [7:0]                                                      wb_dat_i;
319
output [7:0]                                                     wb_dat_o;
320
input                                                                   wb_we_i;
321
input                                                                   wb_re_i;
322
output                                                                  stx_pad_o;
323
input                                                                   srx_pad_i;
324
input [3:0]                                                      modem_inputs;
325
output                                                                  rts_pad_o;
326
output                                                                  dtr_pad_o;
327
output                                                                  int_o;
328
wire [3:0]                                                               modem_inputs;
329
reg                                                                             enable;
330
wire                                                                            stx_pad_o;
331
wire                                                                            srx_pad_i;
332
wire                                                                            srx_pad;
333
reg [7:0]                                                                wb_dat_o;
334
wire [3-1:0]             wb_addr_i;
335
wire [7:0]                                                               wb_dat_i;
336
reg [3:0]                                                                ier;
337
reg [3:0]                                                                iir;
338
reg [1:0]                                                                fcr;
339
reg [4:0]                                                                mcr;
340
reg [7:0]                                                                lcr;
341
reg [7:0]                                                                msr;
342
reg [15:0]                                                               dl;
343
reg [7:0]                                                                scratch;
344
reg                                                                             start_dlc;
345
reg                                                                             lsr_mask_d;
346
reg                                                                             msi_reset;
347
reg [15:0]                                                               dlc;
348
reg                                                                             int_o;
349
reg [3:0]                                                                trigger_level;
350
reg                                                                             rx_reset;
351
reg                                                                             tx_reset;
352
wire                                                                            dlab;
353
wire                                                                            cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i;
354
wire                                                                            loopback;
355
wire                                                                            cts, dsr, ri, dcd;
356
wire                    cts_c, dsr_c, ri_c, dcd_c;
357
wire                                                                            rts_pad_o, dtr_pad_o;
358
wire [7:0]                                                               lsr;
359
wire                                                                            lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
360
reg                                                                             lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
361
wire                                                                            lsr_mask;
362
assign                                                                  lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
363
assign                                                                  {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
364
assign                                                                  {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
365
assign                  {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[1],mcr[0],mcr[2],mcr[3]}
366
                                                               : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
367
assign                                                                  dlab = lcr[7];
368
assign                                                                  loopback = mcr[4];
369
assign                                                                  rts_pad_o = mcr[1];
370
assign                                                                  dtr_pad_o = mcr[0];
371
wire                                                                            rls_int;
372
wire                                                                            rda_int;
373
wire                                                                            ti_int;
374
wire                                                                            thre_int;
375
wire                                                                            ms_int;
376
reg                                                                             tf_push;
377
reg                                                                             rf_pop;
378
wire [11-1:0]    rf_data_out;
379
wire                                                                            rf_error_bit;
380
wire [5-1:0]     rf_count;
381
wire [5-1:0]     tf_count;
382
wire [2:0]                                                               tstate;
383
wire [3:0]                                                               rstate;
384
wire [9:0]                                                               counter_t;
385
wire                      thre_set_en;
386
reg  [7:0]                block_cnt;
387
reg  [7:0]                block_value;
388
wire serial_out;
389
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
390
  uart_sync_flops    i_uart_sync_flops
391
  (
392
    .rst_i           (wb_rst_i),
393
    .clk_i           (clk),
394
    .stage1_rst_i    (1'b0),
395
    .stage1_clk_en_i (1'b1),
396
    .async_dat_i     (srx_pad_i),
397
    .sync_dat_o      (srx_pad)
398
  );
399
  defparam i_uart_sync_flops.width      = 1;
400
  defparam i_uart_sync_flops.init_value = 1'b1;
401
wire serial_in = loopback ? serial_out : srx_pad;
402
assign stx_pad_o = loopback ? 1'b1 : serial_out;
403
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
404
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
405
always @(dl or dlab or ier or iir or scratch
406
                        or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i)
407
begin
408
        case (wb_addr_i)
409
                3'd0   : wb_dat_o = dlab ? dl[7:0] : rf_data_out[10:3];
410
                3'd1    : wb_dat_o = dlab ? dl[15:8] : ier;
411
                3'd2    : wb_dat_o = {4'b1100,iir};
412
                3'd3    : wb_dat_o = lcr;
413
                3'd5    : wb_dat_o = lsr;
414
                3'd6    : wb_dat_o = msr;
415
                3'd7    : wb_dat_o = scratch;
416
                default:  wb_dat_o = 8'b0;
417
        endcase
418
end
419
always @(posedge clk or posedge wb_rst_i)
420
begin
421
        if (wb_rst_i)
422
                rf_pop <= #1 0;
423
        else
424
        if (rf_pop)
425
                rf_pop <= #1 0;
426
        else
427
        if (wb_re_i && wb_addr_i == 3'd0 && !dlab)
428
                rf_pop <= #1 1;
429
end
430
wire    lsr_mask_condition;
431
wire    iir_read;
432
wire  msr_read;
433
wire    fifo_read;
434
wire    fifo_write;
435
assign lsr_mask_condition = (wb_re_i && wb_addr_i == 3'd5 && !dlab);
436
assign iir_read = (wb_re_i && wb_addr_i == 3'd2 && !dlab);
437
assign msr_read = (wb_re_i && wb_addr_i == 3'd6 && !dlab);
438
assign fifo_read = (wb_re_i && wb_addr_i == 3'd0 && !dlab);
439
assign fifo_write = (wb_we_i && wb_addr_i == 3'd0 && !dlab);
440
always @(posedge clk or posedge wb_rst_i)
441
begin
442
        if (wb_rst_i)
443
                lsr_mask_d <= #1 0;
444
        else
445
                lsr_mask_d <= #1 lsr_mask_condition;
446
end
447
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
448
always @(posedge clk or posedge wb_rst_i)
449
begin
450
        if (wb_rst_i)
451
                msi_reset <= #1 1;
452
        else
453
        if (msi_reset)
454
                msi_reset <= #1 0;
455
        else
456
        if (msr_read)
457
                msi_reset <= #1 1;
458
end
459
always @(posedge clk or posedge wb_rst_i)
460
        if (wb_rst_i)
461
                lcr <= #1 8'b00000011;
462
        else
463
        if (wb_we_i && wb_addr_i==3'd3)
464
                lcr <= #1 wb_dat_i;
465
always @(posedge clk or posedge wb_rst_i)
466
        if (wb_rst_i)
467
        begin
468
                ier <= #1 4'b0000;
469
                dl[15:8] <= #1 8'b0;
470
        end
471
        else
472
        if (wb_we_i && wb_addr_i==3'd1)
473
                if (dlab)
474
                begin
475
                        dl[15:8] <= #1 wb_dat_i;
476
                end
477
                else
478
                        ier <= #1 wb_dat_i[3:0];
479
always @(posedge clk or posedge wb_rst_i)
480
        if (wb_rst_i) begin
481
                fcr <= #1 2'b11;
482
                rx_reset <= #1 0;
483
                tx_reset <= #1 0;
484
        end else
485
        if (wb_we_i && wb_addr_i==3'd2) begin
486
                fcr <= #1 wb_dat_i[7:6];
487
                rx_reset <= #1 wb_dat_i[1];
488
                tx_reset <= #1 wb_dat_i[2];
489
        end else begin
490
                rx_reset <= #1 0;
491
                tx_reset <= #1 0;
492
        end
493
always @(posedge clk or posedge wb_rst_i)
494
        if (wb_rst_i)
495
                mcr <= #1 5'b0;
496
        else
497
        if (wb_we_i && wb_addr_i==3'd4)
498
                        mcr <= #1 wb_dat_i[4:0];
499
always @(posedge clk or posedge wb_rst_i)
500
        if (wb_rst_i)
501
                scratch <= #1 0;
502
        else
503
        if (wb_we_i && wb_addr_i==3'd7)
504
                scratch <= #1 wb_dat_i;
505
always @(posedge clk or posedge wb_rst_i)
506
        if (wb_rst_i)
507
        begin
508
                dl[7:0]  <= #1 8'b0;
509
                tf_push   <= #1 1'b0;
510
                start_dlc <= #1 1'b0;
511
        end
512
        else
513
        if (wb_we_i && wb_addr_i==3'd0)
514
                if (dlab)
515
                begin
516
                        dl[7:0] <= #1 wb_dat_i;
517
                        start_dlc <= #1 1'b1;
518
                        tf_push <= #1 1'b0;
519
                end
520
                else
521
                begin
522
                        tf_push   <= #1 1'b1;
523
                        start_dlc <= #1 1'b0;
524
                end
525
        else
526
        begin
527
                start_dlc <= #1 1'b0;
528
                tf_push   <= #1 1'b0;
529
        end
530
always @(fcr)
531
        case (fcr[1:0])
532
                2'b00 : trigger_level = 1;
533
                2'b01 : trigger_level = 4;
534
                2'b10 : trigger_level = 8;
535
                2'b11 : trigger_level = 14;
536
        endcase
537
reg [3:0] delayed_modem_signals;
538
always @(posedge clk or posedge wb_rst_i)
539
begin
540
        if (wb_rst_i)
541
          begin
542
                msr <= #1 0;
543
                delayed_modem_signals[3:0] <= #1 0;
544
          end
545
        else begin
546
                msr[3:0] <= #1 msi_reset ? 4'b0 :
547
                        msr[3:0] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
548
                msr[7:4] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
549
                delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
550
        end
551
end
552
assign lsr0 = (rf_count==0 && rf_push_pulse);
553
assign lsr1 = rf_overrun;
554
assign lsr2 = rf_data_out[1];
555
assign lsr3 = rf_data_out[0];
556
assign lsr4 = rf_data_out[2];
557
assign lsr5 = (tf_count==5'b0 && thre_set_en);
558
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate ==  0));
559
assign lsr7 = rf_error_bit | rf_overrun;
560
reg      lsr0_d;
561
always @(posedge clk or posedge wb_rst_i)
562
        if (wb_rst_i) lsr0_d <= #1 0;
563
        else lsr0_d <= #1 lsr0;
564
always @(posedge clk or posedge wb_rst_i)
565
        if (wb_rst_i) lsr0r <= #1 0;
566
        else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 :
567
                                          lsr0r || (lsr0 && ~lsr0_d);
568
reg lsr1_d;
569
always @(posedge clk or posedge wb_rst_i)
570
        if (wb_rst_i) lsr1_d <= #1 0;
571
        else lsr1_d <= #1 lsr1;
572
always @(posedge clk or posedge wb_rst_i)
573
        if (wb_rst_i) lsr1r <= #1 0;
574
        else    lsr1r <= #1     lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d);
575
reg lsr2_d;
576
always @(posedge clk or posedge wb_rst_i)
577
        if (wb_rst_i) lsr2_d <= #1 0;
578
        else lsr2_d <= #1 lsr2;
579
always @(posedge clk or posedge wb_rst_i)
580
        if (wb_rst_i) lsr2r <= #1 0;
581
        else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d);
582
reg lsr3_d;
583
always @(posedge clk or posedge wb_rst_i)
584
        if (wb_rst_i) lsr3_d <= #1 0;
585
        else lsr3_d <= #1 lsr3;
586
always @(posedge clk or posedge wb_rst_i)
587
        if (wb_rst_i) lsr3r <= #1 0;
588
        else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d);
589
reg lsr4_d;
590
always @(posedge clk or posedge wb_rst_i)
591
        if (wb_rst_i) lsr4_d <= #1 0;
592
        else lsr4_d <= #1 lsr4;
593
always @(posedge clk or posedge wb_rst_i)
594
        if (wb_rst_i) lsr4r <= #1 0;
595
        else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
596
reg lsr5_d;
597
always @(posedge clk or posedge wb_rst_i)
598
        if (wb_rst_i) lsr5_d <= #1 1;
599
        else lsr5_d <= #1 lsr5;
600
always @(posedge clk or posedge wb_rst_i)
601
        if (wb_rst_i) lsr5r <= #1 1;
602
        else lsr5r <= #1 (fifo_write) ? 0 :  lsr5r || (lsr5 && ~lsr5_d);
603
reg lsr6_d;
604
always @(posedge clk or posedge wb_rst_i)
605
        if (wb_rst_i) lsr6_d <= #1 1;
606
        else lsr6_d <= #1 lsr6;
607
always @(posedge clk or posedge wb_rst_i)
608
        if (wb_rst_i) lsr6r <= #1 1;
609
        else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
610
reg lsr7_d;
611
always @(posedge clk or posedge wb_rst_i)
612
        if (wb_rst_i) lsr7_d <= #1 0;
613
        else lsr7_d <= #1 lsr7;
614
always @(posedge clk or posedge wb_rst_i)
615
        if (wb_rst_i) lsr7r <= #1 0;
616
        else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
617
always @(posedge clk or posedge wb_rst_i)
618
begin
619
        if (wb_rst_i)
620
                dlc <= #1 0;
621
        else
622
                if (start_dlc | ~ (|dlc))
623
                        dlc <= #1 dl - 1;
624
                else
625
                        dlc <= #1 dlc - 1;
626
end
627
always @(posedge clk or posedge wb_rst_i)
628
begin
629
        if (wb_rst_i)
630
                enable <= #1 1'b0;
631
        else
632
                if (|dl & ~(|dlc))
633
                        enable <= #1 1'b1;
634
                else
635
                        enable <= #1 1'b0;
636
end
637
always @(lcr)
638
  case (lcr[3:0])
639
    4'b0000                             : block_value =  95;
640
    4'b0100                             : block_value = 103;
641
    4'b0001, 4'b1000                    : block_value = 111;
642
    4'b1100                             : block_value = 119;
643
    4'b0010, 4'b0101, 4'b1001           : block_value = 127;
644
    4'b0011, 4'b0110, 4'b1010, 4'b1101  : block_value = 143;
645
    4'b0111, 4'b1011, 4'b1110           : block_value = 159;
646
    4'b1111                             : block_value = 175;
647
  endcase
648
always @(posedge clk or posedge wb_rst_i)
649
begin
650
  if (wb_rst_i)
651
    block_cnt <= #1 8'd0;
652
  else
653
  if(lsr5r & fifo_write)
654
    block_cnt <= #1 block_value;
655
  else
656
  if (enable & block_cnt != 8'b0)
657
    block_cnt <= #1 block_cnt - 1;
658
end
659
assign thre_set_en = ~(|block_cnt);
660
assign rls_int  = ier[2] && (lsr[1] || lsr[2] || lsr[3] || lsr[4]);
661
assign rda_int  = ier[0] && (rf_count >= {1'b0,trigger_level});
662
assign thre_int = ier[1] && lsr[5];
663
assign ms_int   = ier[3] && (| msr[3:0]);
664
assign ti_int   = ier[0] && (counter_t == 10'b0) && (|rf_count);
665
reg      rls_int_d;
666
reg      thre_int_d;
667
reg      ms_int_d;
668
reg      ti_int_d;
669
reg      rda_int_d;
670
always  @(posedge clk or posedge wb_rst_i)
671
        if (wb_rst_i) rls_int_d <= #1 0;
672
        else rls_int_d <= #1 rls_int;
673
always  @(posedge clk or posedge wb_rst_i)
674
        if (wb_rst_i) rda_int_d <= #1 0;
675
        else rda_int_d <= #1 rda_int;
676
always  @(posedge clk or posedge wb_rst_i)
677
        if (wb_rst_i) thre_int_d <= #1 0;
678
        else thre_int_d <= #1 thre_int;
679
always  @(posedge clk or posedge wb_rst_i)
680
        if (wb_rst_i) ms_int_d <= #1 0;
681
        else ms_int_d <= #1 ms_int;
682
always  @(posedge clk or posedge wb_rst_i)
683
        if (wb_rst_i) ti_int_d <= #1 0;
684
        else ti_int_d <= #1 ti_int;
685
wire     rls_int_rise;
686
wire     thre_int_rise;
687
wire     ms_int_rise;
688
wire     ti_int_rise;
689
wire     rda_int_rise;
690
assign rda_int_rise    = rda_int & ~rda_int_d;
691
assign rls_int_rise       = rls_int & ~rls_int_d;
692
assign thre_int_rise   = thre_int & ~thre_int_d;
693
assign ms_int_rise        = ms_int & ~ms_int_d;
694
assign ti_int_rise        = ti_int & ~ti_int_d;
695
reg     rls_int_pnd;
696
reg     rda_int_pnd;
697
reg     thre_int_pnd;
698
reg     ms_int_pnd;
699
reg     ti_int_pnd;
700
always  @(posedge clk or posedge wb_rst_i)
701
        if (wb_rst_i) rls_int_pnd <= #1 0;
702
        else
703
                rls_int_pnd <= #1 lsr_mask ? 0 :
704
                                                        rls_int_rise ? 1 :
705
                                                        rls_int_pnd && ier[2];
706
always  @(posedge clk or posedge wb_rst_i)
707
        if (wb_rst_i) rda_int_pnd <= #1 0;
708
        else
709
                rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 :
710
                                                        rda_int_rise ? 1 :
711
                                                        rda_int_pnd && ier[0];
712
always  @(posedge clk or posedge wb_rst_i)
713
        if (wb_rst_i) thre_int_pnd <= #1 0;
714
        else
715
                thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[0] & iir[3:1] == 3'b001)? 0 :
716
                                                        thre_int_rise ? 1 :
717
                                                        thre_int_pnd && ier[1];
718
always  @(posedge clk or posedge wb_rst_i)
719
        if (wb_rst_i) ms_int_pnd <= #1 0;
720
        else
721
                ms_int_pnd <= #1 msr_read ? 0 :
722
                                                        ms_int_rise ? 1 :
723
                                                        ms_int_pnd && ier[3];
724
always  @(posedge clk or posedge wb_rst_i)
725
        if (wb_rst_i) ti_int_pnd <= #1 0;
726
        else
727
                ti_int_pnd <= #1 fifo_read ? 0 :
728
                                                        ti_int_rise ? 1 :
729
                                                        ti_int_pnd && ier[0];
730
always @(posedge clk or posedge wb_rst_i)
731
begin
732
        if (wb_rst_i)
733
                int_o <= #1 1'b0;
734
        else
735
                int_o <= #1
736
                                        rls_int_pnd             ?       ~lsr_mask                                       :
737
                                        rda_int_pnd             ? 1                                                             :
738
                                        ti_int_pnd              ? ~fifo_read                                    :
739
                                        thre_int_pnd    ? !(fifo_write & iir_read) :
740
                                        ms_int_pnd              ? ~msr_read                                             :
741
                                        0;
742
end
743
always @(posedge clk or posedge wb_rst_i)
744
begin
745
        if (wb_rst_i)
746
                iir <= #1 1;
747
        else
748
        if (rls_int_pnd)
749
        begin
750
                iir[3:1] <= #1 3'b011;
751
                iir[0] <= #1 1'b0;
752
        end else
753
        if (rda_int)
754
        begin
755
                iir[3:1] <= #1 3'b010;
756
                iir[0] <= #1 1'b0;
757
        end
758
        else if (ti_int_pnd)
759
        begin
760
                iir[3:1] <= #1 3'b110;
761
                iir[0] <= #1 1'b0;
762
        end
763
        else if (thre_int_pnd)
764
        begin
765
                iir[3:1] <= #1 3'b001;
766
                iir[0] <= #1 1'b0;
767
        end
768
        else if (ms_int_pnd)
769
        begin
770
                iir[3:1] <= #1 3'b000;
771
                iir[0] <= #1 1'b0;
772
        end else
773
        begin
774
                iir[3:1] <= #1 0;
775
                iir[0] <= #1 1'b1;
776
        end
777
end
778
endmodule
779
`timescale 1ns/10ps
780
module uart_rfifo (clk,
781
        wb_rst_i, data_in, data_out,
782
        push,
783
        pop,
784
        overrun,
785
        count,
786
        error_bit,
787
        fifo_reset,
788
        reset_status
789
        );
790
parameter fifo_width = 8;
791
parameter fifo_depth = 16;
792
parameter fifo_pointer_w = 4;
793
parameter fifo_counter_w = 5;
794
input                           clk;
795
input                           wb_rst_i;
796
input                           push;
797
input                           pop;
798
input   [fifo_width-1:0] data_in;
799
input                           fifo_reset;
800
input       reset_status;
801
output  [fifo_width-1:0] data_out;
802
output                          overrun;
803
output  [fifo_counter_w-1:0]     count;
804
output                          error_bit;
805
wire    [fifo_width-1:0] data_out;
806
wire [7:0] data8_out;
807
reg     [2:0]    fifo[fifo_depth-1:0];
808
reg     [fifo_pointer_w-1:0]     top;
809
reg     [fifo_pointer_w-1:0]     bottom;
810
reg     [fifo_counter_w-1:0]     count;
811
reg                             overrun;
812
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
813
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
814
        (.clk(clk),
815
                        .we(push),
816
                        .a(top),
817
                        .dpra(bottom),
818
                        .di(data_in[fifo_width-1:fifo_width-8]),
819
                        .dpo(data8_out)
820
                );
821
always @(posedge clk or posedge wb_rst_i)
822
begin
823
        if (wb_rst_i)
824
        begin
825
                top             <= #1 0;
826
                bottom          <= #1 1'b0;
827
                count           <= #1 0;
828
                fifo[0] <= #1 0;
829
                fifo[1] <= #1 0;
830
                fifo[2] <= #1 0;
831
                fifo[3] <= #1 0;
832
                fifo[4] <= #1 0;
833
                fifo[5] <= #1 0;
834
                fifo[6] <= #1 0;
835
                fifo[7] <= #1 0;
836
                fifo[8] <= #1 0;
837
                fifo[9] <= #1 0;
838
                fifo[10] <= #1 0;
839
                fifo[11] <= #1 0;
840
                fifo[12] <= #1 0;
841
                fifo[13] <= #1 0;
842
                fifo[14] <= #1 0;
843
                fifo[15] <= #1 0;
844
        end
845
        else
846
        if (fifo_reset) begin
847
                top             <= #1 0;
848
                bottom          <= #1 1'b0;
849
                count           <= #1 0;
850
                fifo[0] <= #1 0;
851
                fifo[1] <= #1 0;
852
                fifo[2] <= #1 0;
853
                fifo[3] <= #1 0;
854
                fifo[4] <= #1 0;
855
                fifo[5] <= #1 0;
856
                fifo[6] <= #1 0;
857
                fifo[7] <= #1 0;
858
                fifo[8] <= #1 0;
859
                fifo[9] <= #1 0;
860
                fifo[10] <= #1 0;
861
                fifo[11] <= #1 0;
862
                fifo[12] <= #1 0;
863
                fifo[13] <= #1 0;
864
                fifo[14] <= #1 0;
865
                fifo[15] <= #1 0;
866
        end
867
  else
868
        begin
869
                case ({push, pop})
870
                2'b10 : if (count<fifo_depth)
871
                        begin
872
                                top       <= #1 top_plus_1;
873
                                fifo[top] <= #1 data_in[2:0];
874
                                count     <= #1 count + 1'b1;
875
                        end
876
                2'b01 : if(count>0)
877
                        begin
878
        fifo[bottom] <= #1 0;
879
                                bottom   <= #1 bottom + 1'b1;
880
                                count    <= #1 count - 1'b1;
881
                        end
882
                2'b11 : begin
883
                                bottom   <= #1 bottom + 1'b1;
884
                                top       <= #1 top_plus_1;
885
                                fifo[top] <= #1 data_in[2:0];
886
                        end
887
    default: ;
888
                endcase
889
        end
890
end
891
always @(posedge clk or posedge wb_rst_i)
892
begin
893
  if (wb_rst_i)
894
    overrun   <= #1 1'b0;
895
  else
896
  if(fifo_reset | reset_status)
897
    overrun   <= #1 1'b0;
898
  else
899
  if(push & ~pop & (count==fifo_depth))
900
    overrun   <= #1 1'b1;
901
end
902
assign data_out = {data8_out,fifo[bottom]};
903
wire    [2:0]    word0 = fifo[0];
904
wire    [2:0]    word1 = fifo[1];
905
wire    [2:0]    word2 = fifo[2];
906
wire    [2:0]    word3 = fifo[3];
907
wire    [2:0]    word4 = fifo[4];
908
wire    [2:0]    word5 = fifo[5];
909
wire    [2:0]    word6 = fifo[6];
910
wire    [2:0]    word7 = fifo[7];
911
wire    [2:0]    word8 = fifo[8];
912
wire    [2:0]    word9 = fifo[9];
913
wire    [2:0]    word10 = fifo[10];
914
wire    [2:0]    word11 = fifo[11];
915
wire    [2:0]    word12 = fifo[12];
916
wire    [2:0]    word13 = fifo[13];
917
wire    [2:0]    word14 = fifo[14];
918
wire    [2:0]    word15 = fifo[15];
919
assign  error_bit = |(word0[2:0]  | word1[2:0]  | word2[2:0]  | word3[2:0]  |
920
                              word4[2:0]  | word5[2:0]  | word6[2:0]  | word7[2:0]  |
921
                              word8[2:0]  | word9[2:0]  | word10[2:0] | word11[2:0] |
922
                              word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
923
endmodule
924
`timescale 1ns/10ps
925
module uart_tfifo (clk,
926
        wb_rst_i, data_in, data_out,
927
        push,
928
        pop,
929
        overrun,
930
        count,
931
        fifo_reset,
932
        reset_status
933
        );
934
parameter fifo_width = 8;
935
parameter fifo_depth = 16;
936
parameter fifo_pointer_w = 4;
937
parameter fifo_counter_w = 5;
938
input                           clk;
939
input                           wb_rst_i;
940
input                           push;
941
input                           pop;
942
input   [fifo_width-1:0] data_in;
943
input                           fifo_reset;
944
input       reset_status;
945
output  [fifo_width-1:0] data_out;
946
output                          overrun;
947
output  [fifo_counter_w-1:0]     count;
948
wire    [fifo_width-1:0] data_out;
949
reg     [fifo_pointer_w-1:0]     top;
950
reg     [fifo_pointer_w-1:0]     bottom;
951
reg     [fifo_counter_w-1:0]     count;
952
reg                             overrun;
953
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
954
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
955
        (.clk(clk),
956
                        .we(push),
957
                        .a(top),
958
                        .dpra(bottom),
959
                        .di(data_in),
960
                        .dpo(data_out)
961
                );
962
always @(posedge clk or posedge wb_rst_i)
963
begin
964
        if (wb_rst_i)
965
        begin
966
                top             <= #1 0;
967
                bottom          <= #1 1'b0;
968
                count           <= #1 0;
969
        end
970
        else
971
        if (fifo_reset) begin
972
                top             <= #1 0;
973
                bottom          <= #1 1'b0;
974
                count           <= #1 0;
975
        end
976
  else
977
        begin
978
                case ({push, pop})
979
                2'b10 : if (count<fifo_depth)
980
                        begin
981
                                top       <= #1 top_plus_1;
982
                                count     <= #1 count + 1'b1;
983
                        end
984
                2'b01 : if(count>0)
985
                        begin
986
                                bottom   <= #1 bottom + 1'b1;
987
                                count    <= #1 count - 1'b1;
988
                        end
989
                2'b11 : begin
990
                                bottom   <= #1 bottom + 1'b1;
991
                                top       <= #1 top_plus_1;
992
                        end
993
    default: ;
994
                endcase
995
        end
996
end
997
always @(posedge clk or posedge wb_rst_i)
998
begin
999
  if (wb_rst_i)
1000
    overrun   <= #1 1'b0;
1001
  else
1002
  if(fifo_reset | reset_status)
1003
    overrun   <= #1 1'b0;
1004
  else
1005
  if(push & (count==fifo_depth))
1006
    overrun   <= #1 1'b1;
1007
end
1008
endmodule
1009
`timescale 1ns/10ps
1010
module uart_sync_flops
1011
(
1012
  rst_i,
1013
  clk_i,
1014
  stage1_rst_i,
1015
  stage1_clk_en_i,
1016
  async_dat_i,
1017
  sync_dat_o
1018
);
1019
parameter Tp            = 1;
1020
parameter width         = 1;
1021
parameter init_value    = 1'b0;
1022
input                           rst_i;
1023
input                           clk_i;
1024
input                           stage1_rst_i;
1025
input                           stage1_clk_en_i;
1026
input   [width-1:0]             async_dat_i;
1027
output  [width-1:0]             sync_dat_o;
1028
reg     [width-1:0]             sync_dat_o;
1029
reg     [width-1:0]             flop_0;
1030
always @ (posedge clk_i or posedge rst_i)
1031
begin
1032
    if (rst_i)
1033
        flop_0 <= #Tp {width{init_value}};
1034
    else
1035
        flop_0 <= #Tp async_dat_i;
1036
end
1037
always @ (posedge clk_i or posedge rst_i)
1038
begin
1039
    if (rst_i)
1040
        sync_dat_o <= #Tp {width{init_value}};
1041
    else if (stage1_rst_i)
1042
        sync_dat_o <= #Tp {width{init_value}};
1043
    else if (stage1_clk_en_i)
1044
        sync_dat_o <= #Tp flop_0;
1045
end
1046
endmodule
1047
`timescale 1ns/10ps
1048
module uart_wb (clk, wb_rst_i,
1049
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
1050
        wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
1051
        we_o, re_o
1052
);
1053
input             clk;
1054
input             wb_rst_i;
1055
input             wb_we_i;
1056
input             wb_stb_i;
1057
input             wb_cyc_i;
1058
input [3:0]   wb_sel_i;
1059
input [3-1:0]    wb_adr_i;
1060
input [7:0]  wb_dat_i;
1061
output [7:0] wb_dat_o;
1062
reg [7:0]         wb_dat_o;
1063
wire [7:0]        wb_dat_i;
1064
reg [7:0]         wb_dat_is;
1065
output [3-1:0]   wb_adr_int;
1066
input [7:0]   wb_dat8_o;
1067
output [7:0]  wb_dat8_i;
1068
input [31:0]  wb_dat32_o;
1069
output            wb_ack_o;
1070
output            we_o;
1071
output            re_o;
1072
wire                      we_o;
1073
reg                       wb_ack_o;
1074
reg [7:0]          wb_dat8_i;
1075
wire [7:0]         wb_dat8_o;
1076
wire [3-1:0]     wb_adr_int;
1077
reg [3-1:0]      wb_adr_is;
1078
reg                                                             wb_we_is;
1079
reg                                                             wb_cyc_is;
1080
reg                                                             wb_stb_is;
1081
reg [3:0]                                                wb_sel_is;
1082
wire [3:0]   wb_sel_i;
1083
reg                      wre ;
1084
reg [1:0]         wbstate;
1085
always  @(posedge clk or posedge wb_rst_i)
1086
        if (wb_rst_i) begin
1087
                wb_ack_o <= #1 1'b0;
1088
                wbstate <= #1 0;
1089
                wre <= #1 1'b1;
1090
        end else
1091
                case (wbstate)
1092
                        0: begin
1093
                                if (wb_stb_is & wb_cyc_is) begin
1094
                                        wre <= #1 0;
1095
                                        wbstate <= #1 1;
1096
                                        wb_ack_o <= #1 1;
1097
                                end else begin
1098
                                        wre <= #1 1;
1099
                                        wb_ack_o <= #1 0;
1100
                                end
1101
                        end
1102
                        1: begin
1103
                           wb_ack_o <= #1 0;
1104
                                wbstate <= #1 2;
1105
                                wre <= #1 0;
1106
                        end
1107
                        2,3: begin
1108
                                wb_ack_o <= #1 0;
1109
                                wbstate <= #1 0;
1110
                                wre <= #1 0;
1111
                        end
1112
                endcase
1113
assign we_o =  wb_we_is & wb_stb_is & wb_cyc_is & wre ;
1114
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ;
1115
always  @(posedge clk or posedge wb_rst_i)
1116
        if (wb_rst_i) begin
1117
                wb_adr_is <= #1 0;
1118
                wb_we_is <= #1 0;
1119
                wb_cyc_is <= #1 0;
1120
                wb_stb_is <= #1 0;
1121
                wb_dat_is <= #1 0;
1122
                wb_sel_is <= #1 0;
1123
        end else begin
1124
                wb_adr_is <= #1 wb_adr_i;
1125
                wb_we_is <= #1 wb_we_i;
1126
                wb_cyc_is <= #1 wb_cyc_i;
1127
                wb_stb_is <= #1 wb_stb_i;
1128
                wb_dat_is <= #1 wb_dat_i;
1129
                wb_sel_is <= #1 wb_sel_i;
1130
        end
1131
always @(posedge clk or posedge wb_rst_i)
1132
        if (wb_rst_i)
1133
                wb_dat_o <= #1 0;
1134
        else
1135
                wb_dat_o <= #1 wb_dat8_o;
1136
always @(wb_dat_is)
1137
        wb_dat8_i = wb_dat_is;
1138
assign wb_adr_int = wb_adr_is;
1139
endmodule
1140
`timescale 1ns/10ps
1141
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
1142
input                                                                           clk;
1143
input                                                                           wb_rst_i;
1144
input [7:0]                                                              lcr;
1145
input                                                                           tf_push;
1146
input [7:0]                                                              wb_dat_i;
1147
input                                                                           enable;
1148
input                                                                           tx_reset;
1149
input                                                                           lsr_mask;
1150
output                                                                          stx_pad_o;
1151
output [2:0]                                                             tstate;
1152
output [5-1:0]   tf_count;
1153
reg [2:0]                                                                        tstate;
1154
reg [4:0]                                                                        counter;
1155
reg [2:0]                                                                        bit_counter;
1156
reg [6:0]                                                                        shift_out;
1157
reg                                                                                     stx_o_tmp;
1158
reg                                                                                     parity_xor;
1159
reg                                                                                     tf_pop;
1160
reg                                                                                     bit_out;
1161
wire [8-1:0]                     tf_data_in;
1162
wire [8-1:0]                     tf_data_out;
1163
wire                                                                                    tf_push;
1164
wire                                                                                    tf_overrun;
1165
wire [5-1:0]             tf_count;
1166
assign                                                                          tf_data_in = wb_dat_i;
1167
uart_tfifo fifo_tx(
1168
        .clk(           clk             ),
1169
        .wb_rst_i(      wb_rst_i        ),
1170
        .data_in(       tf_data_in      ),
1171
        .data_out(      tf_data_out     ),
1172
        .push(          tf_push         ),
1173
        .pop(           tf_pop          ),
1174
        .overrun(       tf_overrun      ),
1175
        .count(         tf_count        ),
1176
        .fifo_reset(    tx_reset        ),
1177
        .reset_status(lsr_mask)
1178
);
1179
parameter s_idle        = 3'd0;
1180
parameter s_send_start  = 3'd1;
1181
parameter s_send_byte   = 3'd2;
1182
parameter s_send_parity = 3'd3;
1183
parameter s_send_stop   = 3'd4;
1184
parameter s_pop_byte    = 3'd5;
1185
always @(posedge clk or posedge wb_rst_i)
1186
begin
1187
  if (wb_rst_i)
1188
  begin
1189
        tstate       <= #1 s_idle;
1190
        stx_o_tmp       <= #1 1'b1;
1191
        counter   <= #1 5'b0;
1192
        shift_out   <= #1 7'b0;
1193
        bit_out     <= #1 1'b0;
1194
        parity_xor  <= #1 1'b0;
1195
        tf_pop      <= #1 1'b0;
1196
        bit_counter <= #1 3'b0;
1197
  end
1198
  else
1199
  if (enable)
1200
  begin
1201
        case (tstate)
1202
        s_idle   :      if (~|tf_count)
1203
                        begin
1204
                                tstate <= #1 s_idle;
1205
                                stx_o_tmp <= #1 1'b1;
1206
                        end
1207
                        else
1208
                        begin
1209
                                tf_pop <= #1 1'b0;
1210
                                stx_o_tmp  <= #1 1'b1;
1211
                                tstate  <= #1 s_pop_byte;
1212
                        end
1213
        s_pop_byte :    begin
1214
                                tf_pop <= #1 1'b1;
1215
                                case (lcr[1:0])
1216
                                2'b00 : begin
1217
                                        bit_counter <= #1 3'b100;
1218
                                        parity_xor  <= #1 ^tf_data_out[4:0];
1219
                                     end
1220
                                2'b01 : begin
1221
                                        bit_counter <= #1 3'b101;
1222
                                        parity_xor  <= #1 ^tf_data_out[5:0];
1223
                                     end
1224
                                2'b10 : begin
1225
                                        bit_counter <= #1 3'b110;
1226
                                        parity_xor  <= #1 ^tf_data_out[6:0];
1227
                                     end
1228
                                2'b11 : begin
1229
                                        bit_counter <= #1 3'b111;
1230
                                        parity_xor  <= #1 ^tf_data_out[7:0];
1231
                                     end
1232
                                endcase
1233
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
1234
                                tstate <= #1 s_send_start;
1235
                        end
1236
        s_send_start :  begin
1237
                                tf_pop <= #1 1'b0;
1238
                                if (~|counter)
1239
                                        counter <= #1 5'b01111;
1240
                                else
1241
                                if (counter == 5'b00001)
1242
                                begin
1243
                                        counter <= #1 0;
1244
                                        tstate <= #1 s_send_byte;
1245
                                end
1246
                                else
1247
                                        counter <= #1 counter - 1'b1;
1248
                                stx_o_tmp <= #1 1'b0;
1249
                        end
1250
        s_send_byte :   begin
1251
                                if (~|counter)
1252
                                        counter <= #1 5'b01111;
1253
                                else
1254
                                if (counter == 5'b00001)
1255
                                begin
1256
                                        if (bit_counter > 3'b0)
1257
                                        begin
1258
                                                bit_counter <= #1 bit_counter - 1'b1;
1259
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
1260
                                                tstate <= #1 s_send_byte;
1261
                                        end
1262
                                        else
1263
                                        if (~lcr[3])
1264
                                        begin
1265
                                                tstate <= #1 s_send_stop;
1266
                                        end
1267
                                        else
1268
                                        begin
1269
                                                case ({lcr[4],lcr[5]})
1270
                                                2'b00:  bit_out <= #1 ~parity_xor;
1271
                                                2'b01:  bit_out <= #1 1'b1;
1272
                                                2'b10:  bit_out <= #1 parity_xor;
1273
                                                2'b11:  bit_out <= #1 1'b0;
1274
                                                endcase
1275
                                                tstate <= #1 s_send_parity;
1276
                                        end
1277
                                        counter <= #1 0;
1278
                                end
1279
                                else
1280
                                        counter <= #1 counter - 1'b1;
1281
                                stx_o_tmp <= #1 bit_out;
1282
                        end
1283
        s_send_parity : begin
1284
                                if (~|counter)
1285
                                        counter <= #1 5'b01111;
1286
                                else
1287
                                if (counter == 5'b00001)
1288
                                begin
1289
                                        counter <= #1 4'b0;
1290
                                        tstate <= #1 s_send_stop;
1291
                                end
1292
                                else
1293
                                        counter <= #1 counter - 1'b1;
1294
                                stx_o_tmp <= #1 bit_out;
1295
                        end
1296
        s_send_stop :  begin
1297
                                if (~|counter)
1298
                                  begin
1299
                                                casex ({lcr[2],lcr[1:0]})
1300
                                                3'b0xx:   counter <= #1 5'b01101;
1301
                                                3'b100:   counter <= #1 5'b10101;
1302
                                                default:          counter <= #1 5'b11101;
1303
                                                endcase
1304
                                        end
1305
                                else
1306
                                if (counter == 5'b00001)
1307
                                begin
1308
                                        counter <= #1 0;
1309
                                        tstate <= #1 s_idle;
1310
                                end
1311
                                else
1312
                                        counter <= #1 counter - 1'b1;
1313
                                stx_o_tmp <= #1 1'b1;
1314
                        end
1315
                default :
1316
                        tstate <= #1 s_idle;
1317
        endcase
1318
  end
1319
  else
1320
    tf_pop <= #1 1'b0;
1321
end
1322
assign stx_pad_o = lcr[6] ? 1'b0 : stx_o_tmp;
1323
endmodule
1324
`timescale 1ns/10ps
1325
module uart_top (
1326
        wb_clk_i,
1327
        wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
1328
        int_o,
1329
        stx_pad_o, srx_pad_i,
1330
        rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
1331
        );
1332
parameter                                                        uart_data_width = 8;
1333
parameter                                                        uart_addr_width = 3;
1334
input                                                            wb_clk_i;
1335
input                                                            wb_rst_i;
1336
input [uart_addr_width-1:0]       wb_adr_i;
1337
input [uart_data_width-1:0]       wb_dat_i;
1338
output [uart_data_width-1:0]      wb_dat_o;
1339
input                                                            wb_we_i;
1340
input                                                            wb_stb_i;
1341
input                                                            wb_cyc_i;
1342
input [3:0]                                                       wb_sel_i;
1343
output                                                           wb_ack_o;
1344
output                                                           int_o;
1345
input                                                            srx_pad_i;
1346
output                                                           stx_pad_o;
1347
output                                                           rts_pad_o;
1348
input                                                            cts_pad_i;
1349
output                                                           dtr_pad_o;
1350
input                                                            dsr_pad_i;
1351
input                                                            ri_pad_i;
1352
input                                                            dcd_pad_i;
1353
wire                                                                     stx_pad_o;
1354
wire                                                                     rts_pad_o;
1355
wire                                                                     dtr_pad_o;
1356
wire [uart_addr_width-1:0]        wb_adr_i;
1357
wire [uart_data_width-1:0]        wb_dat_i;
1358
wire [uart_data_width-1:0]        wb_dat_o;
1359
wire [7:0]                                                        wb_dat8_i;
1360
wire [7:0]                                                        wb_dat8_o;
1361
wire [31:0]                                               wb_dat32_o;
1362
wire [3:0]                                                        wb_sel_i;
1363
wire [uart_addr_width-1:0]        wb_adr_int;
1364
wire                                                                     we_o;
1365
wire                                 re_o;
1366
uart_wb         wb_interface(
1367
                .clk(           wb_clk_i                ),
1368
                .wb_rst_i(      wb_rst_i        ),
1369
        .wb_dat_i(wb_dat_i),
1370
        .wb_dat_o(wb_dat_o),
1371
        .wb_dat8_i(wb_dat8_i),
1372
        .wb_dat8_o(wb_dat8_o),
1373
         .wb_dat32_o(32'b0),
1374
         .wb_sel_i(4'b0),
1375
                .wb_we_i(       wb_we_i         ),
1376
                .wb_stb_i(      wb_stb_i        ),
1377
                .wb_cyc_i(      wb_cyc_i        ),
1378
                .wb_ack_o(      wb_ack_o        ),
1379
        .wb_adr_i(wb_adr_i),
1380
        .wb_adr_int(wb_adr_int),
1381
                .we_o(          we_o            ),
1382
                .re_o(re_o)
1383
                );
1384
uart_regs       regs(
1385
        .clk(           wb_clk_i                ),
1386
        .wb_rst_i(      wb_rst_i        ),
1387
        .wb_addr_i(     wb_adr_int      ),
1388
        .wb_dat_i(      wb_dat8_i       ),
1389
        .wb_dat_o(      wb_dat8_o       ),
1390
        .wb_we_i(       we_o            ),
1391
   .wb_re_i(re_o),
1392
        .modem_inputs(  {cts_pad_i, dsr_pad_i,
1393
        ri_pad_i,  dcd_pad_i}   ),
1394
        .stx_pad_o(             stx_pad_o               ),
1395
        .srx_pad_i(             srx_pad_i               ),
1396
        .rts_pad_o(             rts_pad_o               ),
1397
        .dtr_pad_o(             dtr_pad_o               ),
1398
        .int_o(         int_o           )
1399
);
1400
initial
1401
begin
1402
                $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
1403
                $display("(%m) UART INFO: Doesn't have baudrate output\n");
1404
end
1405
endmodule
1406
`endif
1407
module versatile_io (
1408
    input [31:0] wbs_dat_i,
1409
    input [31:0] wbs_adr_i,
1410
    input [3:0] wbs_sel_i,
1411
    input wbs_we_i, wbs_stb_i, wbs_cyc_i,
1412
    output [31:0] wbs_dat_o,
1413
    output wbs_ack_o,
1414
`ifdef B4
1415
    output wbs_stall_o,
1416
`endif
1417
`include "versatile_io_module.v"
1418
`ifdef UART0
1419
    output uart0_irq,
1420
`endif
1421
    input wbs_clk, wbs_rst,
1422
    input clk, rst
1423
);
1424
 
1425
`ifdef UART0
1426
parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI;
1427
parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO;
1428
parameter [31:0] uart0_base_adr = `UART0_BASE_ADR;
1429
`endif
1430
function [7:0] tobyte;
1431
input [3:0] sel_i;
1432
input [31:0] dat_i;
1433
begin
1434
    tobyte = ({8{sel_i[3]}} & dat_i[31:24]) | ({8{sel_i[2]}} & dat_i[23:16]) | ({8{sel_i[1]}} & dat_i[15:8]) | ({8{sel_i[0]}} & dat_i[7:0]);
1435
end
1436
endfunction
1437
 
1438
function [31:0] toword;
1439
input [7:0] dat_i;
1440
begin
1441
    toword = {4{dat_i}};
1442
end
1443
endfunction
1444
 
1445
function [31:0] mask;
1446
input [31:0] dat_i;
1447
input sel;
1448
begin
1449
    mask = {32{sel}} & dat_i;
1450
end
1451
endfunction
1452
 
1453
`ifdef UART0
1454
wire uart0_cs;
1455
assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo];
1456
wire [7:0] uart0_temp;
1457
wire uart0_ack_o;
1458
uart_top uart0  (
1459
    .wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst),
1460
    // Wishbone signals
1461
    .wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0),
1462
    .int_o(uart0_irq), // interrupt request
1463
    // UART     signals
1464
    // serial input/output
1465
    .stx_pad_o(uart0_tx_pad_i), .srx_pad_i(uart0_rx_pad_i),
1466
    // modem signals
1467
    .rts_pad_o(), .cts_pad_i(1'b0), .dtr_pad_o(), .dsr_pad_i(1'b0), .ri_pad_i(1'b0), .dcd_pad_i(1'b0) );
1468
assign uart0_dat_o = mask( toword(uart0_temp), uart0_ack_o);
1469
`else
1470
assign uart0_dat_o = 32'h0;
1471
assign uart0_ack_o = 1'b0;
1472
`endif
1473
 
1474
assign wbs_dat_o = uart0_dat_o;
1475
assign wbs_ack_o = uart0_ack_o;
1476
`ifdef WB4
1477
assign wbs_stall_o = 1'b0;
1478
`endif
1479
 
1480
endmodule

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