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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_module.v] - Blame information for rev 11

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`include "versatile_io_defines.v"
`ifdef UART0
    input uart0_rx_pad_i,
    output uart0_tx_pad_o,
`endif
`ifdef UART1
    input uart1_rx_pad_i,
    output uart1_tx_pad_o,
`endif

Line No.	Rev	Author	Line
1	2	unneback	`include "versatile_io_defines.v"
2			`ifdef UART0
3			`input uart0_rx_pad_i,`
4	11	unneback	`output uart0_tx_pad_o,`
5	2	unneback	`endif
6	6	unneback	`ifdef UART1
7			`input uart1_rx_pad_i,`
8	11	unneback	`output uart1_tx_pad_o,`
9	6	unneback	`endif

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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_module.v] - Blame information for rev 11