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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_module_inst.v] - Blame information for rev 10

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Line No. Rev Author Line
1 2 unneback
`include "versatile_io_defines.v"
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versatile_io vio0 (
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    .wbs_dat_i(wbs_vio_dat_i),
5 10 unneback
    .wbs_adr_i(wbs_vio_adr_i),
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    .wbs_sel_i(wbs_vio_sel_i),
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    .wbs_we_i(wbs_vio_we_i),
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    .wbs_stb_i(wbs_vio_stb_i),
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    .wbs_cyc_i(wbs_vio_cyc_i),
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    .wbs_dat_o(wbs_vio_dat_o),
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    .wbs_ack_o(wbs_vio_ack_o),
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`ifdef B4
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    .wbs_stall_o(wbs_vio_stall_o),
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`endif
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`ifdef UART0
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    .uart0_rx_pad_i(uart0_rx_pad_i),
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    .uart0_tx_pad_i(uart0_tx_pad_i),
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    .uart0_irq(vio_uart0_irq),
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`endif
20 6 unneback
`ifdef UART1
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    .uart1_rx_pad_i(uart1_rx_pad_i),
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    .uart1_tx_pad_i(uart1_tx_pad_i),
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    .uart1_irq(vio_uart1_irq),
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`endif
25 2 unneback
    .wbs_clk(wb_clk), .wbs_rst(wb_rst),
26 10 unneback
    .clk(clk33), .rst(rst33));

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