URL https://opencores.org/ocsvn/versatile_io/versatile_io/trunk

Subversion Repositories versatile_io

[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_wires.v] - Blame information for rev 6

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`include "versatile_io_defines.v"
wire [31:0] wbs_vio_dat_i;
wire [31:0] wbs_vio_adr_i;
wire  [3:0] wbs_vio_sel_i;
wire wbs_vio_we_i, wbs_vio_stb_i, wbs_vio_cyc_i;
wire [31:0] wbs_vio_dat_o;
wire wbs_vio_ack_o, wbs_vio_err_o;
`ifdef B4
wire wbs_vio_stall_o;
`endif
`ifdef UART0
wire vio_uart0_irq;
`endif
`ifdef UART1
wire vio_uart1_irq;
`endif

Line No.	Rev	Author	Line
1	2	unneback	`include "versatile_io_defines.v"
2			`wire [31:0] wbs_vio_dat_i;`
3			`wire [31:0] wbs_vio_adr_i;`
4			`wire [3:0] wbs_vio_sel_i;`
5			`wire wbs_vio_we_i, wbs_vio_stb_i, wbs_vio_cyc_i;`
6			`wire [31:0] wbs_vio_dat_o;`
7			`wire wbs_vio_ack_o, wbs_vio_err_o;`
8			`ifdef B4
9			`wire wbs_vio_stall_o;`
10			`endif
11			`ifdef UART0
12			`wire vio_uart0_irq;`
13			`endif
14	6	unneback	`ifdef UART1
15			`wire vio_uart1_irq;`
16			`endif

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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_wires.v] - Blame information for rev 6