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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Blame information for rev 139

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, counters                                 ////
////                                                              ////
////  Description                                                 ////
////  counters                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more counters                                        ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef CNT_SHREG_WRAP
`define MODULE cnt_shreg_wrap
module `BASE`MODULE ( q, rst, clk);
`undef MODULE
 
   parameter length = 4;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        q <= {q[length-1],q[0:length-2]};
 
endmodule
`endif
 
`ifdef CNT_SHREG_CE_WRAP
`define MODULE cnt_shreg_ce_wrap
module `BASE`MODULE ( cke, q, rst, clk);
`undef MODULE
 
   parameter length = 4;
   input cke;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            q <= {q[length-1],q[0:length-2]};
 
endmodule
`endif
 
`ifdef CNT_SHREG_CLEAR
`define MODULE cnt_shreg_clear
module `BASE`MODULE ( clear, q, rst, clk);
`undef MODULE
 
   parameter length = 4;
   input clear;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (clear)
            q <= {1'b1,{length-1{1'b0}}};
        else
            q <= q >> 1;
 
endmodule
`endif
 
`ifdef CNT_SHREG_CE_CLEAR
`define MODULE cnt_shreg_ce_clear
module `BASE`MODULE ( cke, clear, q, rst, clk);
`undef MODULE
 
   parameter length = 4;
   input cke, clear;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
            else
                q <= q >> 1;
 
endmodule
`endif
 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
`define MODULE cnt_shreg_ce_clear_wrap
module `BASE`MODULE ( cke, clear, q, rst, clk);
`undef MODULE
 
   parameter length = 4;
   input cke, clear;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
            else
            q <= {q[length-1],q[0:length-2]};
 
endmodule
`endif

Line No.	Rev	Author	Line
1	3	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, counters ////`
4			`//// ////`
5			`//// Description ////`
6			`//// counters ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more counters ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef CNT_SHREG_WRAP
44			`define MODULE cnt_shreg_wrap
45			module `BASE`MODULE ( q, rst, clk);
46			`undef MODULE
47	4	unneback
48			`parameter length = 4;`
49	5	unneback	`output reg [0:length-1] q;`
50			`input rst;`
51			`input clk;`
52
53			`always @ (posedge clk or posedge rst)`
54			`if (rst)`
55			`q <= {1'b1,{length-1{1'b0}}};`
56			`else`
57			`q <= {q[length-1],q[0:length-2]};`
58
59			`endmodule`
60	40	unneback	`endif
61	5	unneback
62	40	unneback	`ifdef CNT_SHREG_CE_WRAP
63			`define MODULE cnt_shreg_ce_wrap
64			module `BASE`MODULE ( cke, q, rst, clk);
65			`undef MODULE
66	5	unneback
67			`parameter length = 4;`
68	4	unneback	`input cke;`
69			`output reg [0:length-1] q;`
70			`input rst;`
71			`input clk;`
72
73			`always @ (posedge clk or posedge rst)`
74			`if (rst)`
75			`q <= {1'b1,{length-1{1'b0}}};`
76			`else`
77			`if (cke)`
78	5	unneback	`q <= {q[length-1],q[0:length-2]};`
79	4	unneback
80			`endmodule`
81	40	unneback	`endif
82	4	unneback
83	104	unneback	`ifdef CNT_SHREG_CLEAR
84			`define MODULE cnt_shreg_clear
85			module `BASE`MODULE ( clear, q, rst, clk);
86			`undef MODULE
87
88			`parameter length = 4;`
89			`input clear;`
90			`output reg [0:length-1] q;`
91			`input rst;`
92			`input clk;`
93
94			`always @ (posedge clk or posedge rst)`
95			`if (rst)`
96			`q <= {1'b1,{length-1{1'b0}}};`
97			`else`
98			`if (clear)`
99			`q <= {1'b1,{length-1{1'b0}}};`
100			`else`
101			`q <= q >> 1;`
102
103			`endmodule`
104			`endif
105
106	40	unneback	`ifdef CNT_SHREG_CE_CLEAR
107			`define MODULE cnt_shreg_ce_clear
108			module `BASE`MODULE ( cke, clear, q, rst, clk);
109			`undef MODULE
110	4	unneback
111			`parameter length = 4;`
112	5	unneback	`input cke, clear;`
113	4	unneback	`output reg [0:length-1] q;`
114			`input rst;`
115			`input clk;`
116
117			`always @ (posedge clk or posedge rst)`
118			`if (rst)`
119			`q <= {1'b1,{length-1{1'b0}}};`
120			`else`
121			`if (cke)`
122			`if (clear)`
123			`q <= {1'b1,{length-1{1'b0}}};`
124			`else`
125			`q <= q >> 1;`
126
127			`endmodule`
128	40	unneback	`endif
129	4	unneback
130	40	unneback	`ifdef CNT_SHREG_CE_CLEAR_WRAP
131			`define MODULE cnt_shreg_ce_clear_wrap
132			module `BASE`MODULE ( cke, clear, q, rst, clk);
133			`undef MODULE
134	4	unneback
135	5	unneback	`parameter length = 4;`
136			`input cke, clear;`
137			`output reg [0:length-1] q;`
138			`input rst;`
139			`input clk;`
140
141			`always @ (posedge clk or posedge rst)`
142			`if (rst)`
143			`q <= {1'b1,{length-1{1'b0}}};`
144			`else`
145			`if (cke)`
146			`if (clear)`
147			`q <= {1'b1,{length-1{1'b0}}};`
148			`else`
149			`q <= {q[length-1],q[0:length-2]};`
150
151			`endmodule`
152	40	unneback	`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Blame information for rev 139