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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, counters                                 ////
////                                                              ////
////  Description                                                 ////
////  counters                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more counters                                        ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module cnt_shreg_wrap ( q, rst, clk);
 
   parameter length = 4;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        q <= {q[length-1],q[0:length-2]};
 
endmodule
 
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
 
   parameter length = 4;
   input cke;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            q <= {q[length-1],q[0:length-2]};
 
endmodule
 
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
 
   parameter length = 4;
   input cke, clear;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
            else
                q <= q >> 1;
 
endmodule
 
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
 
   parameter length = 4;
   input cke, clear;
   output reg [0:length-1] q;
   input rst;
   input clk;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
    else
        if (cke)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
            else
            q <= {q[length-1],q[0:length-2]};
 
endmodule

Line No.	Rev	Author	Line
1	3	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, counters ////`
4			`//// ////`
5			`//// Description ////`
6			`//// counters ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more counters ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	5	unneback	`module cnt_shreg_wrap ( q, rst, clk);`
44	4	unneback
45			`parameter length = 4;`
46	5	unneback	`output reg [0:length-1] q;`
47			`input rst;`
48			`input clk;`
49
50			`always @ (posedge clk or posedge rst)`
51			`if (rst)`
52			`q <= {1'b1,{length-1{1'b0}}};`
53			`else`
54			`q <= {q[length-1],q[0:length-2]};`
55
56			`endmodule`
57
58			`module cnt_shreg_ce_wrap ( cke, q, rst, clk);`
59
60			`parameter length = 4;`
61	4	unneback	`input cke;`
62			`output reg [0:length-1] q;`
63			`input rst;`
64			`input clk;`
65
66			`always @ (posedge clk or posedge rst)`
67			`if (rst)`
68			`q <= {1'b1,{length-1{1'b0}}};`
69			`else`
70			`if (cke)`
71	5	unneback	`q <= {q[length-1],q[0:length-2]};`
72	4	unneback
73			`endmodule`
74
75			`module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`
76
77			`parameter length = 4;`
78	5	unneback	`input cke, clear;`
79	4	unneback	`output reg [0:length-1] q;`
80			`input rst;`
81			`input clk;`
82
83			`always @ (posedge clk or posedge rst)`
84			`if (rst)`
85			`q <= {1'b1,{length-1{1'b0}}};`
86			`else`
87			`if (cke)`
88			`if (clear)`
89			`q <= {1'b1,{length-1{1'b0}}};`
90			`else`
91			`q <= q >> 1;`
92
93			`endmodule`
94
95	5	unneback	`module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);`
96	4	unneback
97	5	unneback	`parameter length = 4;`
98			`input cke, clear;`
99			`output reg [0:length-1] q;`
100			`input rst;`
101			`input clk;`
102
103			`always @ (posedge clk or posedge rst)`
104			`if (rst)`
105			`q <= {1'b1,{length-1{1'b0}}};`
106			`else`
107			`if (cke)`
108			`if (clear)`
109			`q <= {1'b1,{length-1{1'b0}}};`
110			`else`
111			`q <= {q[length-1],q[0:length-2]};`
112
113			`endmodule`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Blame information for rev 7