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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 101

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29			`define SHIFT_UNIT_32
30			`define LOGIC_UNIT
31
32			`define CNT_SHREG_WRAP
33			`define CNT_SHREG_CE_WRAP
34			`define CNT_SHREG_CE_CLEAR
35			`define CNT_SHREG_CE_CLEAR_WRAP
36
37			`define MUX_ANDOR
38			`define MUX2_ANDOR
39			`define MUX3_ANDOR
40			`define MUX4_ANDOR
41			`define MUX5_ANDOR
42			`define MUX6_ANDOR
43	43	unneback	`define PARITY
44	40	unneback
45			`define ROM_INIT
46			`define RAM
47			`define RAM_BE
48			`define DPRAM_1R1W
49			`define DPRAM_2R1W
50	100	unneback	`define DPRAM_1R2W
51	40	unneback	`define DPRAM_2R2W
52	75	unneback	`define DPRAM_BE_2R2W
53	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
54			`define FIFO_2R2W_SYNC_SIMPLEX
55			`define FIFO_CMP_ASYNC
56			`define FIFO_1R1W_ASYNC
57			`define FIFO_2R2W_ASYNC
58			`define FIFO_2R2W_ASYNC_SIMPLEX
59	48	unneback	`define REG_FILE
60	40	unneback
61			`define DFF
62			`define DFF_ARRAY
63			`define DFF_CE
64			`define DFF_CE_CLEAR
65			`define DF_CE_SET
66			`define SPR
67			`define SRP
68			`define DFF_SR
69			`define LATCH
70			`define SHREG
71			`define SHREG_CE
72			`define DELAY
73			`define DELAY_EMPTYFLAG
74	94	unneback	`define PULSE2TOGGLE
75			`define TOGGLE2PULSE
76			`define SYNCHRONIZER
77			`define CDC
78	40	unneback
79	75	unneback	`define WB3AVALON_BRIDGE
80	40	unneback	`define WB3WB3_BRIDGE
81			`define WB3_ARBITER_TYPE1
82	83	unneback	`define WB_ADR_INC
83	101	unneback	`define WB_RAM
84	48	unneback	`define WB_B4_ROM
85	40	unneback	`define WB_BOOT_ROM
86			`define WB_DPRAM
87	101	unneback	`define WB_CACHE
88	40	unneback
89	44	unneback	`define IO_DFF_OE
90			`define O_DFF
91
92	40	unneback	`endif
93
94			`ifdef PLL
95			`ifndef SYNC_RST
96			`define SYNC_RST
97			`endif
98			`endif
99
100			`ifdef SYNC_RST
101			`ifndef GBUF
102			`define GBUF
103			`endif
104			`endif
105
106	92	unneback	`ifdef WB_B3_DPRAM
107			`ifndef WB_ADR_INC
108			`define WB_ADR_INC
109	40	unneback	`endif
110	92	unneback	`ifndef DPRAM_BE_2R2W
111			`define DPRAM_BE_2R2W
112	40	unneback	`endif
113			`endif
114
115	101	unneback	`ifdef WB_RAM
116	83	unneback	`ifndef WB_ADR_INC
117			`define WB_ADR_INC
118	62	unneback	`endif
119			`ifndef RAM_BE
120			`define RAM_BE
121			`endif
122			`endif
123
124	40	unneback	`ifdef WB3_ARBITER_TYPE1
125	42	unneback	`ifndef SPR
126			`define SPR
127			`endif
128	40	unneback	`ifndef MUX_ANDOR
129			`define MUX_ANDOR
130			`endif
131			`endif
132
133	76	unneback	`ifdef WB3AVALON_BRIDGE
134			`ifndef WB3WB3_BRIDGE
135			`define WB3WB3_BRIDGE
136			`endif
137			`endif
138
139	40	unneback	`ifdef WB3WB3_BRIDGE
140			`ifndef CNT_SHREG_CE_CLEAR
141			`define CNT_SHREG_CE_CLEAR
142			`endif
143			`ifndef DFF
144			`define DFF
145			`endif
146			`ifndef DFF_CE
147			`define DFF_CE
148			`endif
149			`ifndef CNT_SHREG_CE_CLEAR
150			`define CNT_SHREG_CE_CLEAR
151			`endif
152			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
153			`define FIFO_2R2W_ASYNC_SIMPLEX
154			`endif
155			`endif
156
157	101	unneback	`ifdef WB_CACHE
158	100	unneback	`ifndef RAM
159			`define RAM
160			`endif
161			`ifndef WB_ADR_INC
162			`define WB_ADR_INC
163			`endif
164			`ifndef DPRAM_1R1W
165			`define DPRAM_1R1W
166			`endif
167			`ifndef DPRAM_1R2W
168			`define DPRAM_1R2W
169			`endif
170			`ifndef DPRAM_BE_2R2W
171			`define DPRAM_BE_2R2W
172			`endif
173			`ifndef CDC
174			`define CDC
175			`endif
176			`endif
177	97	unneback
178	40	unneback	`ifdef MULTS18X18
179			`ifndef MULTS
180			`define MULTS
181			`endif
182			`endif
183
184			`ifdef SHIFT_UNIT_32
185			`ifndef MULTS
186			`define MULTS
187			`endif
188			`endif
189
190			`ifdef MUX2_ANDOR
191			`ifndef MUX_ANDOR
192			`define MUX_ANDOR
193			`endif
194			`endif
195
196			`ifdef MUX3_ANDOR
197			`ifndef MUX_ANDOR
198			`define MUX_ANDOR
199			`endif
200			`endif
201
202			`ifdef MUX4_ANDOR
203			`ifndef MUX_ANDOR
204			`define MUX_ANDOR
205			`endif
206			`endif
207
208			`ifdef MUX5_ANDOR
209			`ifndef MUX_ANDOR
210			`define MUX_ANDOR
211			`endif
212			`endif
213
214			`ifdef MUX6_ANDOR
215			`ifndef MUX_ANDOR
216			`define MUX_ANDOR
217			`endif
218			`endif
219
220			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
221			`ifndef CNT_BIN_CE
222			`define CNT_BIN_CE
223			`endif
224			`ifndef DPRAM_1R1W
225			`define DPRAM_1R1W
226			`endif
227			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
228			`define CNT_BIN_CE_REW_Q_ZQ_L1
229			`endif
230			`endif
231
232			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
233			`ifndef CNT_LFSR_CE
234			`define CNT_LFSR_CE
235			`endif
236			`ifndef DPRAM_2R2W
237			`define DPRAM_2R2W
238			`endif
239			`ifndef CNT_BIN_CE_REW_ZQ_L1
240			`define CNT_BIN_CE_REW_ZQ_L1
241			`endif
242			`endif
243
244			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
245			`ifndef CNT_GRAY_CE_BIN
246			`define CNT_GRAY_CE_BIN
247			`endif
248			`ifndef DPRAM_2R2W
249			`define DPRAM_2R2W
250			`endif
251			`ifndef FIFO_CMP_ASYNC
252			`define FIFO_CMP_ASYNC
253			`endif
254			`endif
255
256			`ifdef FIFO_2R2W_ASYNC
257			`ifndef FIFO_1R1W_ASYNC
258			`define FIFO_1R1W_ASYNC
259			`endif
260			`endif
261
262			`ifdef FIFO_1R1W_ASYNC
263			`ifndef CNT_GRAY_CE_BIN
264			`define CNT_GRAY_CE_BIN
265			`endif
266			`ifndef DPRAM_1R1W
267			`define DPRAM_1R1W
268			`endif
269			`ifndef FIFO_CMP_ASYNC
270			`define FIFO_CMP_ASYNC
271			`endif
272			`endif
273
274			`ifdef FIFO_CMP_ASYNC
275			`ifndef DFF_SR
276			`define DFF_SR
277			`endif
278			`ifndef DFF
279			`define DFF
280			`endif
281			`endif
282	48	unneback
283			`ifdef REG_FILE
284			`ifndef DPRAM_1R1W
285			`define DPRAM_1R1W
286			`endif
287			`endif
288	97	unneback
289	98	unneback	`ifdef CDC
290			`ifndef PULSE2TOGGLE
291			`define PULSE2TOGGLE
292			`endif
293			`ifndef TOGGLE2PULSE
294			`define TOGGLE2PULSE
295			`endif
296			`ifndef SYNCHRONIZER
297			`define SYNCHRONIZER
298			`endif
299			`endif
300
301	97	unneback	`// size to width`
302	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 101