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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 137

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
`define WB_SDR_SDRAM_CTRL
 
`define IO_DFF_OE
`define O_DFF
`define O_DDR
`define O_CLK
 
`endif
 
///////////////////////////////////////
// dependencies
///////////////////////////////////////
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_SDR_SDRAM_CTRL
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_SDR_SDRAM
`define WB_SDR_SDRAM
`endif
`ifndef IO_DFF_OE
`define IO_DFF_OE
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SDR_SDRAM
`ifndef CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`endif
`ifndef CNT_LFSR_ZQ
`define CNT_LFSR_ZQ
`endif
`ifndef DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef O_CLK
`ifndef O_DDR
`define O_DDR
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29			`define SHIFT_UNIT_32
30			`define LOGIC_UNIT
31
32			`define CNT_SHREG_WRAP
33			`define CNT_SHREG_CE_WRAP
34	104	unneback	`define CNT_SHREG_CLEAR
35	40	unneback	`define CNT_SHREG_CE_CLEAR
36			`define CNT_SHREG_CE_CLEAR_WRAP
37
38			`define MUX_ANDOR
39			`define MUX2_ANDOR
40			`define MUX3_ANDOR
41			`define MUX4_ANDOR
42			`define MUX5_ANDOR
43			`define MUX6_ANDOR
44	43	unneback	`define PARITY
45	40	unneback
46			`define ROM_INIT
47			`define RAM
48			`define RAM_BE
49			`define DPRAM_1R1W
50			`define DPRAM_2R1W
51	100	unneback	`define DPRAM_1R2W
52	40	unneback	`define DPRAM_2R2W
53	75	unneback	`define DPRAM_BE_2R2W
54	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
55			`define FIFO_2R2W_SYNC_SIMPLEX
56			`define FIFO_CMP_ASYNC
57			`define FIFO_1R1W_ASYNC
58			`define FIFO_2R2W_ASYNC
59			`define FIFO_2R2W_ASYNC_SIMPLEX
60	48	unneback	`define REG_FILE
61	40	unneback
62			`define DFF
63			`define DFF_ARRAY
64			`define DFF_CE
65			`define DFF_CE_CLEAR
66			`define DF_CE_SET
67			`define SPR
68			`define SRP
69			`define DFF_SR
70			`define LATCH
71			`define SHREG
72			`define SHREG_CE
73			`define DELAY
74			`define DELAY_EMPTYFLAG
75	94	unneback	`define PULSE2TOGGLE
76			`define TOGGLE2PULSE
77			`define SYNCHRONIZER
78			`define CDC
79	40	unneback
80	75	unneback	`define WB3AVALON_BRIDGE
81	40	unneback	`define WB3WB3_BRIDGE
82			`define WB3_ARBITER_TYPE1
83	83	unneback	`define WB_ADR_INC
84	101	unneback	`define WB_RAM
85	103	unneback	`define WB_SHADOW_RAM
86	48	unneback	`define WB_B4_ROM
87	40	unneback	`define WB_BOOT_ROM
88			`define WB_DPRAM
89	101	unneback	`define WB_CACHE
90	103	unneback	`define WB_AVALON_BRIDGE
91			`define WB_AVALON_MEM_CACHE
92	136	unneback	`define WB_SDR_SDRAM_CTRL
93	40	unneback
94	44	unneback	`define IO_DFF_OE
95			`define O_DFF
96	136	unneback	`define O_DDR
97			`define O_CLK
98	44	unneback
99	40	unneback	`endif
100
101	136	unneback	`///////////////////////////////////////`
102			`// dependencies`
103			`///////////////////////////////////////`
104
105	40	unneback	`ifdef PLL
106			`ifndef SYNC_RST
107			`define SYNC_RST
108			`endif
109			`endif
110
111			`ifdef SYNC_RST
112			`ifndef GBUF
113			`define GBUF
114			`endif
115			`endif
116
117	136	unneback	`ifdef WB_SDR_SDRAM_CTRL
118			`ifndef WB_SHADOW_RAM
119			`define WB_SHADOW_RAM
120			`endif
121			`ifndef WB_CACHE
122			`define WB_CACHE
123			`endif
124			`ifndef WB_SDR_SDRAM
125			`define WB_SDR_SDRAM
126			`endif
127			`ifndef IO_DFF_OE
128			`define IO_DFF_OE
129			`endif
130			`ifndef O_DFF
131			`define O_DFF
132			`endif
133			`ifndef O_CLK
134			`define O_CLK
135			`endif
136			`endif
137
138			`ifdef WB_SDR_SDRAM
139			`ifndef CNT_SHREG_CLEAR
140			`define CNT_SHREG_CLEAR
141			`endif
142			`ifndef CNT_LFSR_ZQ
143			`define CNT_LFSR_ZQ
144			`endif
145			`ifndef DELAY_EMPTYFLAG
146			`define DELAY_EMPTYFLAG
147			`endif
148			`endif
149
150	108	unneback	`ifdef WB_DPRAM
151	92	unneback	`ifndef WB_ADR_INC
152			`define WB_ADR_INC
153	40	unneback	`endif
154	92	unneback	`ifndef DPRAM_BE_2R2W
155			`define DPRAM_BE_2R2W
156	40	unneback	`endif
157			`endif
158
159			`ifdef WB3_ARBITER_TYPE1
160	42	unneback	`ifndef SPR
161			`define SPR
162			`endif
163	40	unneback	`ifndef MUX_ANDOR
164			`define MUX_ANDOR
165			`endif
166			`endif
167
168	76	unneback	`ifdef WB3AVALON_BRIDGE
169			`ifndef WB3WB3_BRIDGE
170			`define WB3WB3_BRIDGE
171			`endif
172			`endif
173
174	40	unneback	`ifdef WB3WB3_BRIDGE
175			`ifndef CNT_SHREG_CE_CLEAR
176			`define CNT_SHREG_CE_CLEAR
177			`endif
178			`ifndef DFF
179			`define DFF
180			`endif
181			`ifndef DFF_CE
182			`define DFF_CE
183			`endif
184			`ifndef CNT_SHREG_CE_CLEAR
185			`define CNT_SHREG_CE_CLEAR
186			`endif
187			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
188			`define FIFO_2R2W_ASYNC_SIMPLEX
189			`endif
190			`endif
191
192	103	unneback
193			`ifdef WB_AVALON_MEM_CACHE
194			`ifndef WB_SHADOW_RAM
195			`define WB_SHADOW_RAM
196			`endif
197			`ifndef WB_CACHE
198			`define WB_CACHE
199			`endif
200			`ifndef WB_AVALON_BRIDGE
201			`define WB_AVALON_BRIDGE
202			`endif
203			`endif
204
205	101	unneback	`ifdef WB_CACHE
206	100	unneback	`ifndef RAM
207			`define RAM
208			`endif
209			`ifndef WB_ADR_INC
210			`define WB_ADR_INC
211			`endif
212			`ifndef DPRAM_1R1W
213			`define DPRAM_1R1W
214			`endif
215			`ifndef DPRAM_1R2W
216			`define DPRAM_1R2W
217			`endif
218			`ifndef DPRAM_BE_2R2W
219			`define DPRAM_BE_2R2W
220			`endif
221			`ifndef CDC
222			`define CDC
223			`endif
224	136	unneback	`ifndef O_DFF
225			`define O_DFF
226	100	unneback	`endif
227	136	unneback	`ifndef O_CLK
228			`define O_CLK
229			`endif
230			`endif
231	103	unneback
232			`ifdef WB_SHADOW_RAM
233	115	unneback	`ifndef WB_RAM
234			`define WB_RAM
235	103	unneback	`endif
236			`endif
237
238			`ifdef WB_RAM
239			`ifndef WB_ADR_INC
240			`define WB_ADR_INC
241			`endif
242	114	unneback	`ifndef RAM_BE
243			`define RAM_BE
244	103	unneback	`endif
245	114	unneback	`endif
246
247	40	unneback	`ifdef MULTS18X18
248			`ifndef MULTS
249			`define MULTS
250			`endif
251			`endif
252
253			`ifdef SHIFT_UNIT_32
254			`ifndef MULTS
255			`define MULTS
256			`endif
257			`endif
258
259			`ifdef MUX2_ANDOR
260			`ifndef MUX_ANDOR
261			`define MUX_ANDOR
262			`endif
263			`endif
264
265			`ifdef MUX3_ANDOR
266			`ifndef MUX_ANDOR
267			`define MUX_ANDOR
268			`endif
269			`endif
270
271			`ifdef MUX4_ANDOR
272			`ifndef MUX_ANDOR
273			`define MUX_ANDOR
274			`endif
275			`endif
276
277			`ifdef MUX5_ANDOR
278			`ifndef MUX_ANDOR
279			`define MUX_ANDOR
280			`endif
281			`endif
282
283			`ifdef MUX6_ANDOR
284			`ifndef MUX_ANDOR
285			`define MUX_ANDOR
286			`endif
287			`endif
288
289			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
290			`ifndef CNT_BIN_CE
291			`define CNT_BIN_CE
292			`endif
293			`ifndef DPRAM_1R1W
294			`define DPRAM_1R1W
295			`endif
296			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
297			`define CNT_BIN_CE_REW_Q_ZQ_L1
298			`endif
299			`endif
300
301			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
302			`ifndef CNT_LFSR_CE
303			`define CNT_LFSR_CE
304			`endif
305			`ifndef DPRAM_2R2W
306			`define DPRAM_2R2W
307			`endif
308			`ifndef CNT_BIN_CE_REW_ZQ_L1
309			`define CNT_BIN_CE_REW_ZQ_L1
310			`endif
311			`endif
312
313			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
314			`ifndef CNT_GRAY_CE_BIN
315			`define CNT_GRAY_CE_BIN
316			`endif
317			`ifndef DPRAM_2R2W
318			`define DPRAM_2R2W
319			`endif
320			`ifndef FIFO_CMP_ASYNC
321			`define FIFO_CMP_ASYNC
322			`endif
323			`endif
324
325			`ifdef FIFO_2R2W_ASYNC
326			`ifndef FIFO_1R1W_ASYNC
327			`define FIFO_1R1W_ASYNC
328			`endif
329			`endif
330
331			`ifdef FIFO_1R1W_ASYNC
332			`ifndef CNT_GRAY_CE_BIN
333			`define CNT_GRAY_CE_BIN
334			`endif
335			`ifndef DPRAM_1R1W
336			`define DPRAM_1R1W
337			`endif
338			`ifndef FIFO_CMP_ASYNC
339			`define FIFO_CMP_ASYNC
340			`endif
341			`endif
342
343			`ifdef FIFO_CMP_ASYNC
344			`ifndef DFF_SR
345			`define DFF_SR
346			`endif
347			`ifndef DFF
348			`define DFF
349			`endif
350			`endif
351	48	unneback
352			`ifdef REG_FILE
353			`ifndef DPRAM_1R1W
354			`define DPRAM_1R1W
355			`endif
356			`endif
357	97	unneback
358	98	unneback	`ifdef CDC
359			`ifndef PULSE2TOGGLE
360			`define PULSE2TOGGLE
361			`endif
362			`ifndef TOGGLE2PULSE
363			`define TOGGLE2PULSE
364			`endif
365			`ifndef SYNCHRONIZER
366			`define SYNCHRONIZER
367			`endif
368			`endif
369
370	136	unneback	`ifdef O_CLK
371			`ifndef O_DDR
372			`define O_DDR
373			`endif
374			`endif
375
376	97	unneback	`// size to width`
377	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 137