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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 139

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define CNT_BIN
`define CNT_BIN_CE
`define CNT_BIN_CLEAR
`define CNT_BIN_CE_CLEAR
`define CNT_BIN_CE_CLEAR_L1_L2
`define CNT_BIN_CE_CLEAR_SET_REW
`define CNT_BIN_CE_REW_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_GRAY
`define CNT_GRAY_CE
`define CNT_GRAY_CE_BIN
`define CNT_LFSR_ZQ
`define CNT_LFSR_CE
`define CNT_LFSR_CE_CLEAR_Q
`define CNT_LFSR_CE_Q
`define CNT_LFSR_CE_ZQ
`define CNT_LFSR_CE_Q_ZQ
`define CNT_LFSR_CE_REW_L1
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
`define WB_SDR_SDRAM_CTRL
 
`define IO_DFF_OE
`define O_DFF
`define O_DDR
`define O_CLK
 
`endif
 
///////////////////////////////////////
// dependencies
///////////////////////////////////////
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_SDR_SDRAM_CTRL
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_SDR_SDRAM
`define WB_SDR_SDRAM
`endif
`ifndef IO_DFF_OE
`define IO_DFF_OE
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SDR_SDRAM
`ifndef CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`endif
`ifndef CNT_LFSR_ZQ
`define CNT_LFSR_ZQ
`endif
`ifndef DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef O_CLK
`ifndef O_DDR
`define O_DDR
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29			`define SHIFT_UNIT_32
30			`define LOGIC_UNIT
31
32			`define CNT_SHREG_WRAP
33			`define CNT_SHREG_CE_WRAP
34	104	unneback	`define CNT_SHREG_CLEAR
35	40	unneback	`define CNT_SHREG_CE_CLEAR
36			`define CNT_SHREG_CE_CLEAR_WRAP
37
38	139	unneback	`define CNT_BIN
39			`define CNT_BIN_CE
40			`define CNT_BIN_CLEAR
41			`define CNT_BIN_CE_CLEAR
42			`define CNT_BIN_CE_CLEAR_L1_L2
43			`define CNT_BIN_CE_CLEAR_SET_REW
44			`define CNT_BIN_CE_REW_L1
45			`define CNT_BIN_CE_REW_ZQ_L1
46			`define CNT_BIN_CE_REW_Q_ZQ_L1
47			`define CNT_GRAY
48			`define CNT_GRAY_CE
49			`define CNT_GRAY_CE_BIN
50			`define CNT_LFSR_ZQ
51			`define CNT_LFSR_CE
52			`define CNT_LFSR_CE_CLEAR_Q
53			`define CNT_LFSR_CE_Q
54			`define CNT_LFSR_CE_ZQ
55			`define CNT_LFSR_CE_Q_ZQ
56			`define CNT_LFSR_CE_REW_L1
57
58	40	unneback	`define MUX_ANDOR
59			`define MUX2_ANDOR
60			`define MUX3_ANDOR
61			`define MUX4_ANDOR
62			`define MUX5_ANDOR
63			`define MUX6_ANDOR
64	43	unneback	`define PARITY
65	40	unneback
66			`define ROM_INIT
67			`define RAM
68			`define RAM_BE
69			`define DPRAM_1R1W
70			`define DPRAM_2R1W
71	100	unneback	`define DPRAM_1R2W
72	40	unneback	`define DPRAM_2R2W
73	75	unneback	`define DPRAM_BE_2R2W
74	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
75			`define FIFO_2R2W_SYNC_SIMPLEX
76			`define FIFO_CMP_ASYNC
77			`define FIFO_1R1W_ASYNC
78			`define FIFO_2R2W_ASYNC
79			`define FIFO_2R2W_ASYNC_SIMPLEX
80	48	unneback	`define REG_FILE
81	40	unneback
82			`define DFF
83			`define DFF_ARRAY
84			`define DFF_CE
85			`define DFF_CE_CLEAR
86			`define DF_CE_SET
87			`define SPR
88			`define SRP
89			`define DFF_SR
90			`define LATCH
91			`define SHREG
92			`define SHREG_CE
93			`define DELAY
94			`define DELAY_EMPTYFLAG
95	94	unneback	`define PULSE2TOGGLE
96			`define TOGGLE2PULSE
97			`define SYNCHRONIZER
98			`define CDC
99	40	unneback
100	75	unneback	`define WB3AVALON_BRIDGE
101	40	unneback	`define WB3WB3_BRIDGE
102			`define WB3_ARBITER_TYPE1
103	83	unneback	`define WB_ADR_INC
104	101	unneback	`define WB_RAM
105	103	unneback	`define WB_SHADOW_RAM
106	48	unneback	`define WB_B4_ROM
107	40	unneback	`define WB_BOOT_ROM
108			`define WB_DPRAM
109	101	unneback	`define WB_CACHE
110	103	unneback	`define WB_AVALON_BRIDGE
111			`define WB_AVALON_MEM_CACHE
112	136	unneback	`define WB_SDR_SDRAM_CTRL
113	40	unneback
114	44	unneback	`define IO_DFF_OE
115			`define O_DFF
116	136	unneback	`define O_DDR
117			`define O_CLK
118	44	unneback
119	40	unneback	`endif
120
121	136	unneback	`///////////////////////////////////////`
122			`// dependencies`
123			`///////////////////////////////////////`
124
125	40	unneback	`ifdef PLL
126			`ifndef SYNC_RST
127			`define SYNC_RST
128			`endif
129			`endif
130
131			`ifdef SYNC_RST
132			`ifndef GBUF
133			`define GBUF
134			`endif
135			`endif
136
137	136	unneback	`ifdef WB_SDR_SDRAM_CTRL
138			`ifndef WB_SHADOW_RAM
139			`define WB_SHADOW_RAM
140			`endif
141			`ifndef WB_CACHE
142			`define WB_CACHE
143			`endif
144			`ifndef WB_SDR_SDRAM
145			`define WB_SDR_SDRAM
146			`endif
147			`ifndef IO_DFF_OE
148			`define IO_DFF_OE
149			`endif
150			`ifndef O_DFF
151			`define O_DFF
152			`endif
153			`ifndef O_CLK
154			`define O_CLK
155			`endif
156			`endif
157
158			`ifdef WB_SDR_SDRAM
159			`ifndef CNT_SHREG_CLEAR
160			`define CNT_SHREG_CLEAR
161			`endif
162			`ifndef CNT_LFSR_ZQ
163			`define CNT_LFSR_ZQ
164			`endif
165			`ifndef DELAY_EMPTYFLAG
166			`define DELAY_EMPTYFLAG
167			`endif
168			`endif
169
170	108	unneback	`ifdef WB_DPRAM
171	92	unneback	`ifndef WB_ADR_INC
172			`define WB_ADR_INC
173	40	unneback	`endif
174	92	unneback	`ifndef DPRAM_BE_2R2W
175			`define DPRAM_BE_2R2W
176	40	unneback	`endif
177			`endif
178
179			`ifdef WB3_ARBITER_TYPE1
180	42	unneback	`ifndef SPR
181			`define SPR
182			`endif
183	40	unneback	`ifndef MUX_ANDOR
184			`define MUX_ANDOR
185			`endif
186			`endif
187
188	76	unneback	`ifdef WB3AVALON_BRIDGE
189			`ifndef WB3WB3_BRIDGE
190			`define WB3WB3_BRIDGE
191			`endif
192			`endif
193
194	40	unneback	`ifdef WB3WB3_BRIDGE
195			`ifndef CNT_SHREG_CE_CLEAR
196			`define CNT_SHREG_CE_CLEAR
197			`endif
198			`ifndef DFF
199			`define DFF
200			`endif
201			`ifndef DFF_CE
202			`define DFF_CE
203			`endif
204			`ifndef CNT_SHREG_CE_CLEAR
205			`define CNT_SHREG_CE_CLEAR
206			`endif
207			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
208			`define FIFO_2R2W_ASYNC_SIMPLEX
209			`endif
210			`endif
211
212	103	unneback
213			`ifdef WB_AVALON_MEM_CACHE
214			`ifndef WB_SHADOW_RAM
215			`define WB_SHADOW_RAM
216			`endif
217			`ifndef WB_CACHE
218			`define WB_CACHE
219			`endif
220			`ifndef WB_AVALON_BRIDGE
221			`define WB_AVALON_BRIDGE
222			`endif
223			`endif
224
225	101	unneback	`ifdef WB_CACHE
226	100	unneback	`ifndef RAM
227			`define RAM
228			`endif
229			`ifndef WB_ADR_INC
230			`define WB_ADR_INC
231			`endif
232			`ifndef DPRAM_1R1W
233			`define DPRAM_1R1W
234			`endif
235			`ifndef DPRAM_1R2W
236			`define DPRAM_1R2W
237			`endif
238			`ifndef DPRAM_BE_2R2W
239			`define DPRAM_BE_2R2W
240			`endif
241			`ifndef CDC
242			`define CDC
243			`endif
244	136	unneback	`ifndef O_DFF
245			`define O_DFF
246	100	unneback	`endif
247	136	unneback	`ifndef O_CLK
248			`define O_CLK
249			`endif
250			`endif
251	103	unneback
252			`ifdef WB_SHADOW_RAM
253	115	unneback	`ifndef WB_RAM
254			`define WB_RAM
255	103	unneback	`endif
256			`endif
257
258			`ifdef WB_RAM
259			`ifndef WB_ADR_INC
260			`define WB_ADR_INC
261			`endif
262	114	unneback	`ifndef RAM_BE
263			`define RAM_BE
264	103	unneback	`endif
265	114	unneback	`endif
266
267	40	unneback	`ifdef MULTS18X18
268			`ifndef MULTS
269			`define MULTS
270			`endif
271			`endif
272
273			`ifdef SHIFT_UNIT_32
274			`ifndef MULTS
275			`define MULTS
276			`endif
277			`endif
278
279			`ifdef MUX2_ANDOR
280			`ifndef MUX_ANDOR
281			`define MUX_ANDOR
282			`endif
283			`endif
284
285			`ifdef MUX3_ANDOR
286			`ifndef MUX_ANDOR
287			`define MUX_ANDOR
288			`endif
289			`endif
290
291			`ifdef MUX4_ANDOR
292			`ifndef MUX_ANDOR
293			`define MUX_ANDOR
294			`endif
295			`endif
296
297			`ifdef MUX5_ANDOR
298			`ifndef MUX_ANDOR
299			`define MUX_ANDOR
300			`endif
301			`endif
302
303			`ifdef MUX6_ANDOR
304			`ifndef MUX_ANDOR
305			`define MUX_ANDOR
306			`endif
307			`endif
308
309			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
310			`ifndef CNT_BIN_CE
311			`define CNT_BIN_CE
312			`endif
313			`ifndef DPRAM_1R1W
314			`define DPRAM_1R1W
315			`endif
316			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
317			`define CNT_BIN_CE_REW_Q_ZQ_L1
318			`endif
319			`endif
320
321			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
322			`ifndef CNT_LFSR_CE
323			`define CNT_LFSR_CE
324			`endif
325			`ifndef DPRAM_2R2W
326			`define DPRAM_2R2W
327			`endif
328			`ifndef CNT_BIN_CE_REW_ZQ_L1
329			`define CNT_BIN_CE_REW_ZQ_L1
330			`endif
331			`endif
332
333			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
334			`ifndef CNT_GRAY_CE_BIN
335			`define CNT_GRAY_CE_BIN
336			`endif
337			`ifndef DPRAM_2R2W
338			`define DPRAM_2R2W
339			`endif
340			`ifndef FIFO_CMP_ASYNC
341			`define FIFO_CMP_ASYNC
342			`endif
343			`endif
344
345			`ifdef FIFO_2R2W_ASYNC
346			`ifndef FIFO_1R1W_ASYNC
347			`define FIFO_1R1W_ASYNC
348			`endif
349			`endif
350
351			`ifdef FIFO_1R1W_ASYNC
352			`ifndef CNT_GRAY_CE_BIN
353			`define CNT_GRAY_CE_BIN
354			`endif
355			`ifndef DPRAM_1R1W
356			`define DPRAM_1R1W
357			`endif
358			`ifndef FIFO_CMP_ASYNC
359			`define FIFO_CMP_ASYNC
360			`endif
361			`endif
362
363			`ifdef FIFO_CMP_ASYNC
364			`ifndef DFF_SR
365			`define DFF_SR
366			`endif
367			`ifndef DFF
368			`define DFF
369			`endif
370			`endif
371	48	unneback
372			`ifdef REG_FILE
373			`ifndef DPRAM_1R1W
374			`define DPRAM_1R1W
375			`endif
376			`endif
377	97	unneback
378	98	unneback	`ifdef CDC
379			`ifndef PULSE2TOGGLE
380			`define PULSE2TOGGLE
381			`endif
382			`ifndef TOGGLE2PULSE
383			`define TOGGLE2PULSE
384			`endif
385			`ifndef SYNCHRONIZER
386			`define SYNCHRONIZER
387			`endif
388			`endif
389
390	136	unneback	`ifdef O_CLK
391			`ifndef O_DDR
392			`define O_DDR
393			`endif
394			`endif
395
396	97	unneback	`// size to width`
397	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 139