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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 144

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define ARITH_UNIT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
`define COUNT_UNIT
`define EXT_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define CNT_BIN
`define CNT_BIN_CE
`define CNT_BIN_CLEAR
`define CNT_BIN_CE_CLEAR
`define CNT_BIN_CE_CLEAR_L1_L2
`define CNT_BIN_CE_CLEAR_SET_REW
`define CNT_BIN_CE_REW_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_GRAY
`define CNT_GRAY_CE
`define CNT_GRAY_CE_BIN
`define CNT_LFSR_ZQ
`define CNT_LFSR_CE
`define CNT_LFSR_CE_CLEAR_Q
`define CNT_LFSR_CE_Q
`define CNT_LFSR_CE_ZQ
`define CNT_LFSR_CE_Q_ZQ
`define CNT_LFSR_CE_REW_L1
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
`define WB_SDR_SDRAM_CTRL
 
`define IO_DFF_OE
`define O_DFF
`define O_DDR
`define O_CLK
 
`endif
 
///////////////////////////////////////
// dependencies
///////////////////////////////////////
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_SDR_SDRAM_CTRL
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_SDR_SDRAM
`define WB_SDR_SDRAM
`endif
`ifndef IO_DFF_OE
`define IO_DFF_OE
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SDR_SDRAM
`ifndef CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`endif
`ifndef CNT_LFSR_ZQ
`define CNT_LFSR_ZQ
`endif
`ifndef DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef O_CLK
`ifndef O_DDR
`define O_DDR
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29	140	unneback	`define ARITH_UNIT
30	40	unneback	`define SHIFT_UNIT_32
31			`define LOGIC_UNIT
32	140	unneback	`define COUNT_UNIT
33			`define EXT_UNIT
34	40	unneback
35			`define CNT_SHREG_WRAP
36			`define CNT_SHREG_CE_WRAP
37	104	unneback	`define CNT_SHREG_CLEAR
38	40	unneback	`define CNT_SHREG_CE_CLEAR
39			`define CNT_SHREG_CE_CLEAR_WRAP
40
41	139	unneback	`define CNT_BIN
42			`define CNT_BIN_CE
43			`define CNT_BIN_CLEAR
44			`define CNT_BIN_CE_CLEAR
45			`define CNT_BIN_CE_CLEAR_L1_L2
46			`define CNT_BIN_CE_CLEAR_SET_REW
47			`define CNT_BIN_CE_REW_L1
48			`define CNT_BIN_CE_REW_ZQ_L1
49			`define CNT_BIN_CE_REW_Q_ZQ_L1
50			`define CNT_GRAY
51			`define CNT_GRAY_CE
52			`define CNT_GRAY_CE_BIN
53			`define CNT_LFSR_ZQ
54			`define CNT_LFSR_CE
55			`define CNT_LFSR_CE_CLEAR_Q
56			`define CNT_LFSR_CE_Q
57			`define CNT_LFSR_CE_ZQ
58			`define CNT_LFSR_CE_Q_ZQ
59			`define CNT_LFSR_CE_REW_L1
60
61	40	unneback	`define MUX_ANDOR
62			`define MUX2_ANDOR
63			`define MUX3_ANDOR
64			`define MUX4_ANDOR
65			`define MUX5_ANDOR
66			`define MUX6_ANDOR
67	43	unneback	`define PARITY
68	40	unneback
69			`define ROM_INIT
70			`define RAM
71			`define RAM_BE
72			`define DPRAM_1R1W
73			`define DPRAM_2R1W
74	100	unneback	`define DPRAM_1R2W
75	40	unneback	`define DPRAM_2R2W
76	75	unneback	`define DPRAM_BE_2R2W
77	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
78			`define FIFO_2R2W_SYNC_SIMPLEX
79			`define FIFO_CMP_ASYNC
80			`define FIFO_1R1W_ASYNC
81			`define FIFO_2R2W_ASYNC
82			`define FIFO_2R2W_ASYNC_SIMPLEX
83	48	unneback	`define REG_FILE
84	40	unneback
85			`define DFF
86			`define DFF_ARRAY
87			`define DFF_CE
88			`define DFF_CE_CLEAR
89			`define DF_CE_SET
90			`define SPR
91			`define SRP
92			`define DFF_SR
93			`define LATCH
94			`define SHREG
95			`define SHREG_CE
96			`define DELAY
97			`define DELAY_EMPTYFLAG
98	94	unneback	`define PULSE2TOGGLE
99			`define TOGGLE2PULSE
100			`define SYNCHRONIZER
101			`define CDC
102	40	unneback
103	75	unneback	`define WB3AVALON_BRIDGE
104	40	unneback	`define WB3WB3_BRIDGE
105			`define WB3_ARBITER_TYPE1
106	83	unneback	`define WB_ADR_INC
107	101	unneback	`define WB_RAM
108	103	unneback	`define WB_SHADOW_RAM
109	48	unneback	`define WB_B4_ROM
110	40	unneback	`define WB_BOOT_ROM
111			`define WB_DPRAM
112	101	unneback	`define WB_CACHE
113	103	unneback	`define WB_AVALON_BRIDGE
114			`define WB_AVALON_MEM_CACHE
115	136	unneback	`define WB_SDR_SDRAM_CTRL
116	40	unneback
117	44	unneback	`define IO_DFF_OE
118			`define O_DFF
119	136	unneback	`define O_DDR
120			`define O_CLK
121	44	unneback
122	40	unneback	`endif
123
124	136	unneback	`///////////////////////////////////////`
125			`// dependencies`
126			`///////////////////////////////////////`
127
128	40	unneback	`ifdef PLL
129			`ifndef SYNC_RST
130			`define SYNC_RST
131			`endif
132			`endif
133
134			`ifdef SYNC_RST
135			`ifndef GBUF
136			`define GBUF
137			`endif
138			`endif
139
140	136	unneback	`ifdef WB_SDR_SDRAM_CTRL
141			`ifndef WB_SHADOW_RAM
142			`define WB_SHADOW_RAM
143			`endif
144			`ifndef WB_CACHE
145			`define WB_CACHE
146			`endif
147			`ifndef WB_SDR_SDRAM
148			`define WB_SDR_SDRAM
149			`endif
150			`ifndef IO_DFF_OE
151			`define IO_DFF_OE
152			`endif
153			`ifndef O_DFF
154			`define O_DFF
155			`endif
156			`ifndef O_CLK
157			`define O_CLK
158			`endif
159			`endif
160
161			`ifdef WB_SDR_SDRAM
162			`ifndef CNT_SHREG_CLEAR
163			`define CNT_SHREG_CLEAR
164			`endif
165			`ifndef CNT_LFSR_ZQ
166			`define CNT_LFSR_ZQ
167			`endif
168			`ifndef DELAY_EMPTYFLAG
169			`define DELAY_EMPTYFLAG
170			`endif
171			`endif
172
173	108	unneback	`ifdef WB_DPRAM
174	92	unneback	`ifndef WB_ADR_INC
175			`define WB_ADR_INC
176	40	unneback	`endif
177	141	unneback	`ifndef DFF
178			`define DFF
179			`endif
180	92	unneback	`ifndef DPRAM_BE_2R2W
181			`define DPRAM_BE_2R2W
182	40	unneback	`endif
183			`endif
184
185			`ifdef WB3_ARBITER_TYPE1
186	42	unneback	`ifndef SPR
187			`define SPR
188			`endif
189	40	unneback	`ifndef MUX_ANDOR
190			`define MUX_ANDOR
191			`endif
192			`endif
193
194	76	unneback	`ifdef WB3AVALON_BRIDGE
195			`ifndef WB3WB3_BRIDGE
196			`define WB3WB3_BRIDGE
197			`endif
198			`endif
199
200	40	unneback	`ifdef WB3WB3_BRIDGE
201			`ifndef CNT_SHREG_CE_CLEAR
202			`define CNT_SHREG_CE_CLEAR
203			`endif
204			`ifndef DFF
205			`define DFF
206			`endif
207			`ifndef DFF_CE
208			`define DFF_CE
209			`endif
210			`ifndef CNT_SHREG_CE_CLEAR
211			`define CNT_SHREG_CE_CLEAR
212			`endif
213			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
214			`define FIFO_2R2W_ASYNC_SIMPLEX
215			`endif
216			`endif
217
218	103	unneback
219			`ifdef WB_AVALON_MEM_CACHE
220			`ifndef WB_SHADOW_RAM
221			`define WB_SHADOW_RAM
222			`endif
223			`ifndef WB_CACHE
224			`define WB_CACHE
225			`endif
226			`ifndef WB_AVALON_BRIDGE
227			`define WB_AVALON_BRIDGE
228			`endif
229			`endif
230
231	101	unneback	`ifdef WB_CACHE
232	100	unneback	`ifndef RAM
233			`define RAM
234			`endif
235			`ifndef WB_ADR_INC
236			`define WB_ADR_INC
237			`endif
238			`ifndef DPRAM_1R1W
239			`define DPRAM_1R1W
240			`endif
241			`ifndef DPRAM_1R2W
242			`define DPRAM_1R2W
243			`endif
244			`ifndef DPRAM_BE_2R2W
245			`define DPRAM_BE_2R2W
246			`endif
247			`ifndef CDC
248			`define CDC
249			`endif
250	136	unneback	`ifndef O_DFF
251			`define O_DFF
252	100	unneback	`endif
253	136	unneback	`ifndef O_CLK
254			`define O_CLK
255			`endif
256			`endif
257	103	unneback
258			`ifdef WB_SHADOW_RAM
259	115	unneback	`ifndef WB_RAM
260			`define WB_RAM
261	103	unneback	`endif
262			`endif
263
264			`ifdef WB_RAM
265			`ifndef WB_ADR_INC
266			`define WB_ADR_INC
267			`endif
268	114	unneback	`ifndef RAM_BE
269			`define RAM_BE
270	103	unneback	`endif
271	114	unneback	`endif
272
273	40	unneback	`ifdef MULTS18X18
274			`ifndef MULTS
275			`define MULTS
276			`endif
277			`endif
278
279			`ifdef SHIFT_UNIT_32
280			`ifndef MULTS
281			`define MULTS
282			`endif
283			`endif
284
285			`ifdef MUX2_ANDOR
286			`ifndef MUX_ANDOR
287			`define MUX_ANDOR
288			`endif
289			`endif
290
291			`ifdef MUX3_ANDOR
292			`ifndef MUX_ANDOR
293			`define MUX_ANDOR
294			`endif
295			`endif
296
297			`ifdef MUX4_ANDOR
298			`ifndef MUX_ANDOR
299			`define MUX_ANDOR
300			`endif
301			`endif
302
303			`ifdef MUX5_ANDOR
304			`ifndef MUX_ANDOR
305			`define MUX_ANDOR
306			`endif
307			`endif
308
309			`ifdef MUX6_ANDOR
310			`ifndef MUX_ANDOR
311			`define MUX_ANDOR
312			`endif
313			`endif
314
315			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
316			`ifndef CNT_BIN_CE
317			`define CNT_BIN_CE
318			`endif
319			`ifndef DPRAM_1R1W
320			`define DPRAM_1R1W
321			`endif
322			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
323			`define CNT_BIN_CE_REW_Q_ZQ_L1
324			`endif
325			`endif
326
327			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
328			`ifndef CNT_LFSR_CE
329			`define CNT_LFSR_CE
330			`endif
331			`ifndef DPRAM_2R2W
332			`define DPRAM_2R2W
333			`endif
334			`ifndef CNT_BIN_CE_REW_ZQ_L1
335			`define CNT_BIN_CE_REW_ZQ_L1
336			`endif
337			`endif
338
339			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
340			`ifndef CNT_GRAY_CE_BIN
341			`define CNT_GRAY_CE_BIN
342			`endif
343			`ifndef DPRAM_2R2W
344			`define DPRAM_2R2W
345			`endif
346			`ifndef FIFO_CMP_ASYNC
347			`define FIFO_CMP_ASYNC
348			`endif
349			`endif
350
351			`ifdef FIFO_2R2W_ASYNC
352			`ifndef FIFO_1R1W_ASYNC
353			`define FIFO_1R1W_ASYNC
354			`endif
355			`endif
356
357			`ifdef FIFO_1R1W_ASYNC
358			`ifndef CNT_GRAY_CE_BIN
359			`define CNT_GRAY_CE_BIN
360			`endif
361			`ifndef DPRAM_1R1W
362			`define DPRAM_1R1W
363			`endif
364			`ifndef FIFO_CMP_ASYNC
365			`define FIFO_CMP_ASYNC
366			`endif
367			`endif
368
369			`ifdef FIFO_CMP_ASYNC
370			`ifndef DFF_SR
371			`define DFF_SR
372			`endif
373			`ifndef DFF
374			`define DFF
375			`endif
376			`endif
377	48	unneback
378			`ifdef REG_FILE
379			`ifndef DPRAM_1R1W
380			`define DPRAM_1R1W
381			`endif
382			`endif
383	97	unneback
384	98	unneback	`ifdef CDC
385			`ifndef PULSE2TOGGLE
386			`define PULSE2TOGGLE
387			`endif
388			`ifndef TOGGLE2PULSE
389			`define TOGGLE2PULSE
390			`endif
391			`ifndef SYNCHRONIZER
392			`define SYNCHRONIZER
393			`endif
394			`endif
395
396	136	unneback	`ifdef O_CLK
397			`ifndef O_DDR
398			`define O_DDR
399			`endif
400			`endif
401
402	97	unneback	`// size to width`
403	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 144