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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 72

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B3_RAM_BE
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef SPR
`define SPR
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	40	unneback	`ifdef ALL
14
15			`define GBUF
16			`define SYNC_RST
17			`define PLL
18
19			`define MULTS
20			`define MULTS18X18
21			`define MULT
22			`define SHIFT_UNIT_32
23			`define LOGIC_UNIT
24
25			`define CNT_SHREG_WRAP
26			`define CNT_SHREG_CE_WRAP
27			`define CNT_SHREG_CE_CLEAR
28			`define CNT_SHREG_CE_CLEAR_WRAP
29
30			`define MUX_ANDOR
31			`define MUX2_ANDOR
32			`define MUX3_ANDOR
33			`define MUX4_ANDOR
34			`define MUX5_ANDOR
35			`define MUX6_ANDOR
36	43	unneback	`define PARITY
37	40	unneback
38			`define ROM_INIT
39			`define RAM
40			`define RAM_BE
41			`define DPRAM_1R1W
42			`define DPRAM_2R1W
43			`define DPRAM_2R2W
44			`define FIFO_1R1W_FILL_LEVEL_SYNC
45			`define FIFO_2R2W_SYNC_SIMPLEX
46			`define FIFO_CMP_ASYNC
47			`define FIFO_1R1W_ASYNC
48			`define FIFO_2R2W_ASYNC
49			`define FIFO_2R2W_ASYNC_SIMPLEX
50	48	unneback	`define REG_FILE
51	40	unneback
52			`define DFF
53			`define DFF_ARRAY
54			`define DFF_CE
55			`define DFF_CE_CLEAR
56			`define DF_CE_SET
57			`define SPR
58			`define SRP
59			`define DFF_SR
60			`define LATCH
61			`define SHREG
62			`define SHREG_CE
63			`define DELAY
64			`define DELAY_EMPTYFLAG
65
66			`define WB3WB3_BRIDGE
67			`define WB3_ARBITER_TYPE1
68	59	unneback	`define WB_B3_RAM_BE
69	49	unneback	`define WB_B4_RAM_BE
70	48	unneback	`define WB_B4_ROM
71	40	unneback	`define WB_BOOT_ROM
72			`define WB_DPRAM
73
74	44	unneback	`define IO_DFF_OE
75			`define O_DFF
76
77	40	unneback	`endif
78
79			`ifdef PLL
80			`ifndef SYNC_RST
81			`define SYNC_RST
82			`endif
83			`endif
84
85			`ifdef SYNC_RST
86			`ifndef GBUF
87			`define GBUF
88			`endif
89			`endif
90
91			`ifdef WB_DPRAM
92			`ifndef DPRAM_2R2W
93			`define DPRAM_2R2W
94			`endif
95			`ifndef SPR
96			`define SPR
97			`endif
98			`endif
99
100	62	unneback	`ifdef WB_B3_RAM_BE
101			`ifndef WB3_ARBITER_TYPE1
102			`define WB3_ARBITER_TYPE1
103			`endif
104			`ifndef RAM_BE
105			`define RAM_BE
106			`endif
107			`endif
108
109	40	unneback	`ifdef WB3_ARBITER_TYPE1
110	42	unneback	`ifndef SPR
111			`define SPR
112			`endif
113	40	unneback	`ifndef MUX_ANDOR
114			`define MUX_ANDOR
115			`endif
116			`endif
117
118			`ifdef WB3WB3_BRIDGE
119			`ifndef CNT_SHREG_CE_CLEAR
120			`define CNT_SHREG_CE_CLEAR
121			`endif
122			`ifndef DFF
123			`define DFF
124			`endif
125			`ifndef DFF_CE
126			`define DFF_CE
127			`endif
128			`ifndef CNT_SHREG_CE_CLEAR
129			`define CNT_SHREG_CE_CLEAR
130			`endif
131			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
132			`define FIFO_2R2W_ASYNC_SIMPLEX
133			`endif
134			`endif
135
136			`ifdef MULTS18X18
137			`ifndef MULTS
138			`define MULTS
139			`endif
140			`endif
141
142			`ifdef SHIFT_UNIT_32
143			`ifndef MULTS
144			`define MULTS
145			`endif
146			`endif
147
148			`ifdef MUX2_ANDOR
149			`ifndef MUX_ANDOR
150			`define MUX_ANDOR
151			`endif
152			`endif
153
154			`ifdef MUX3_ANDOR
155			`ifndef MUX_ANDOR
156			`define MUX_ANDOR
157			`endif
158			`endif
159
160			`ifdef MUX4_ANDOR
161			`ifndef MUX_ANDOR
162			`define MUX_ANDOR
163			`endif
164			`endif
165
166			`ifdef MUX5_ANDOR
167			`ifndef MUX_ANDOR
168			`define MUX_ANDOR
169			`endif
170			`endif
171
172			`ifdef MUX6_ANDOR
173			`ifndef MUX_ANDOR
174			`define MUX_ANDOR
175			`endif
176			`endif
177
178			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
179			`ifndef CNT_BIN_CE
180			`define CNT_BIN_CE
181			`endif
182			`ifndef DPRAM_1R1W
183			`define DPRAM_1R1W
184			`endif
185			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
186			`define CNT_BIN_CE_REW_Q_ZQ_L1
187			`endif
188			`endif
189
190			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
191			`ifndef CNT_LFSR_CE
192			`define CNT_LFSR_CE
193			`endif
194			`ifndef DPRAM_2R2W
195			`define DPRAM_2R2W
196			`endif
197			`ifndef CNT_BIN_CE_REW_ZQ_L1
198			`define CNT_BIN_CE_REW_ZQ_L1
199			`endif
200			`endif
201
202			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
203			`ifndef CNT_GRAY_CE_BIN
204			`define CNT_GRAY_CE_BIN
205			`endif
206			`ifndef DPRAM_2R2W
207			`define DPRAM_2R2W
208			`endif
209			`ifndef FIFO_CMP_ASYNC
210			`define FIFO_CMP_ASYNC
211			`endif
212			`endif
213
214			`ifdef FIFO_2R2W_ASYNC
215			`ifndef FIFO_1R1W_ASYNC
216			`define FIFO_1R1W_ASYNC
217			`endif
218			`endif
219
220			`ifdef FIFO_1R1W_ASYNC
221			`ifndef CNT_GRAY_CE_BIN
222			`define CNT_GRAY_CE_BIN
223			`endif
224			`ifndef DPRAM_1R1W
225			`define DPRAM_1R1W
226			`endif
227			`ifndef FIFO_CMP_ASYNC
228			`define FIFO_CMP_ASYNC
229			`endif
230			`endif
231
232			`ifdef FIFO_CMP_ASYNC
233			`ifndef DFF_SR
234			`define DFF_SR
235			`endif
236			`ifndef DFF
237			`define DFF
238			`endif
239			`endif
240	48	unneback
241			`ifdef REG_FILE
242			`ifndef DPRAM_1R1W
243			`define DPRAM_1R1W
244			`endif
245			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 72