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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  IO functions                                                ////
////                                                              ////
////  Description                                                 ////
////  IO functions such as IOB flip-flops                         ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`ifdef O_DFF
`timescale 1ns/1ns
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
input  [width-1:0]  d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
reg  [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin : dffs
    always @ (posedge clk or posedge rst)
    if (rst)
        o_pad_int[i] <= reset_value[i];
    else
        o_pad_int[i] <= d_i_int[i];
    assign #1 o_pad[i] = o_pad_int[i];
end
endgenerate
endmodule
`endif
 
`ifdef IO_DFF_OE
`timescale 1ns/1ns
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = 1'b0;
input  [width-1:0] d_o;
output reg [width-1:0] d_i;
input oe;
inout [width-1:0] io_pad;
input clk, rst;
wire [width-1:0] oe_d `SYN_KEEP;
reg [width-1:0] oe_q;
reg [width-1:0] d_o_q;
assign oe_d = {width{oe}};
genvar i;
generate
for (i=0;i<width;i=i+1) begin : dffs
    always @ (posedge clk or posedge rst)
    if (rst)
        oe_q[i] <= 1'b0;
    else
        oe_q[i] <= oe_d[i];
    always @ (posedge clk or posedge rst)
    if (rst)
        d_o_q[i] <= reset_value;
    else
        d_o_q[i] <= d_o[i];
    always @ (posedge clk or posedge rst)
    if (rst)
        d_i[i] <= reset_value;
    else
        d_i[i] <= io_pad[i];
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule
`endif
 
`ifdef O_DDR
`ifdef ALTERA
`define MODULE o_ddr
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
input  [width-1:0] d_h_i, d_l_i;
output [width-1:0] o_pad;
input clk, rst;
genvar i;
generate
for (i=0;i<width;i=i+1) begin : ddr
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
end
endgenerate
endmodule
`else
`define MODULE o_ddr
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
input  [width-1:0] d_h_i, d_l_i;
output [width-1:0] o_pad;
input clk, rst;
reg [width-1:0] ff1;
reg [width-1:0] ff2;
genvar i;
generate
for (i=0;i<width;i=i+1) begin : ddr
    always @ (posedge clk or posedge rst)
    if (rst)
        ff1[i] <= 1'b0;
    else
        ff1[i] <= d_h_i[i];
    always @ (posedge clk or posedge rst)
    if (rst)
        ff2[i] <= 1'b0;
    else
        ff2[i] <= d_l_i[i];
    assign o_pad = (clk) ? ff1 : ff2;
end
endgenerate
endmodule
`endif
`endif
 
`ifdef O_CLK
`define MODULE o_clk
module `BASE`MODULE ( clk_o_pad, clk, rst);
`undef MODULE
input clk, rst;
output clk_o_pad;
`define MODULE o_ddr
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
`undef MODULE
endmodule
`endif

Line No.	Rev	Author	Line
1	44	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// IO functions ////`
4			`//// ////`
5			`//// Description ////`
6			`//// IO functions such as IOB flip-flops ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42	136	unneback	`ifdef O_DFF
43	45	unneback	`timescale 1ns/1ns
44	44	unneback	`define MODULE o_dff
45			module `BASE`MODULE (d_i, o_pad, clk, rst);
46			`undef MODULE
47			`parameter width = 1;`
48	45	unneback	`parameter reset_value = {width{1'b0}};`
49			`input [width-1:0] d_i;`
50	44	unneback	`output [width-1:0] o_pad;`
51			`input clk, rst;`
52			wire [width-1:0] d_i_int `SYN_KEEP;
53	45	unneback	`reg [width-1:0] o_pad_int;`
54	44	unneback	`assign d_i_int = d_i;`
55			`genvar i;`
56	45	unneback	`generate`
57	136	unneback	`for (i=0;i<width;i=i+1) begin : dffs`
58	44	unneback	`always @ (posedge clk or posedge rst)`
59			`if (rst)`
60	45	unneback	`o_pad_int[i] <= reset_value[i];`
61	44	unneback	`else`
62	45	unneback	`o_pad_int[i] <= d_i_int[i];`
63			`assign #1 o_pad[i] = o_pad_int[i];`
64	44	unneback	`end`
65			`endgenerate`
66			`endmodule`
67			`endif
68
69	136	unneback	`ifdef IO_DFF_OE
70	45	unneback	`timescale 1ns/1ns
71	44	unneback	`define MODULE io_dff_oe
72			module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
73			`undef MODULE
74			`parameter width = 1;`
75	139	unneback	`parameter reset_value = 1'b0;`
76	44	unneback	`input [width-1:0] d_o;`
77			`output reg [width-1:0] d_i;`
78			`input oe;`
79			`inout [width-1:0] io_pad;`
80			`input clk, rst;`
81			wire [width-1:0] oe_d `SYN_KEEP;
82			`reg [width-1:0] oe_q;`
83			`reg [width-1:0] d_o_q;`
84			`assign oe_d = {width{oe}};`
85			`genvar i;`
86			`generate`
87	136	unneback	`for (i=0;i<width;i=i+1) begin : dffs`
88	44	unneback	`always @ (posedge clk or posedge rst)`
89			`if (rst)`
90			`oe_q[i] <= 1'b0;`
91			`else`
92			`oe_q[i] <= oe_d[i];`
93			`always @ (posedge clk or posedge rst)`
94			`if (rst)`
95	139	unneback	`d_o_q[i] <= reset_value;`
96	44	unneback	`else`
97			`d_o_q[i] <= d_o[i];`
98			`always @ (posedge clk or posedge rst)`
99			`if (rst)`
100	139	unneback	`d_i[i] <= reset_value;`
101	44	unneback	`else`
102			`d_i[i] <= io_pad[i];`
103	45	unneback	`assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;`
104	44	unneback	`end`
105			`endgenerate`
106			`endmodule`
107			`endif
108	136	unneback
109			`ifdef O_DDR
110			`ifdef ALTERA
111			`define MODULE o_ddr
112			module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
113			`undef MODULE
114			`parameter width = 1;`
115			`input [width-1:0] d_h_i, d_l_i;`
116			`output [width-1:0] o_pad;`
117			`input clk, rst;`
118			`genvar i;`
119			`generate`
120			`for (i=0;i<width;i=i+1) begin : ddr`
121			`ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );`
122			`end`
123			`endgenerate`
124			`endmodule`
125			`else
126			`define MODULE o_ddr
127			module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
128			`undef MODULE
129			`parameter width = 1;`
130			`input [width-1:0] d_h_i, d_l_i;`
131			`output [width-1:0] o_pad;`
132			`input clk, rst;`
133			`reg [width-1:0] ff1;`
134			`reg [width-1:0] ff2;`
135			`genvar i;`
136			`generate`
137			`for (i=0;i<width;i=i+1) begin : ddr`
138			`always @ (posedge clk or posedge rst)`
139			`if (rst)`
140			`ff1[i] <= 1'b0;`
141			`else`
142			`ff1[i] <= d_h_i[i];`
143			`always @ (posedge clk or posedge rst)`
144			`if (rst)`
145			`ff2[i] <= 1'b0;`
146			`else`
147			`ff2[i] <= d_l_i[i];`
148			`assign o_pad = (clk) ? ff1 : ff2;`
149			`end`
150			`endgenerate`
151			`endmodule`
152			`endif
153			`endif
154
155			`ifdef O_CLK
156			`define MODULE o_clk
157			module `BASE`MODULE ( clk_o_pad, clk, rst);
158			`undef MODULE
159			`input clk, rst;`
160			`output clk_o_pad;`
161			`define MODULE o_ddr
162			`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
163			`undef MODULE
164			`endmodule`
165			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [io.v] - Blame information for rev 145