URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Blame information for rev 148

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [mem_size-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   parameter debug = 0;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [mem_size-1:0];
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    generate
    if (memory_init == 1) begin : init_mem
        initial
            $readmemh(memory_file, ram);
   end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
   end
   endgenerate
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk)
        if (we)
            $display ("Value %h written at address %h : time %t", d, adr, $time);
 
    end
    endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
 
//E2_ifdef SYSTEMVERILOG
    // use a multi-dimensional packed array
    //t o model individual bytes within the word
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
//E2_else
    reg [data_width-1:0] ram [mem_size-1:0];
    wire [data_width/8-1:0] cke;
//E2_endif
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    generate
    if (memory_init == 1) begin : init_mem
        initial
            $readmemh(memory_file, ram);
    end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
    end
   endgenerate
 
//E2_ifdef SYSTEMVERILOG
 
always_ff@(posedge clk)
begin
    if(we) begin
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
        q <= ram[adr];
end
 
//E2_else
 
assign cke = {data_width/8{we}} & be;
   genvar i;
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (cke[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
//E2_endif
 
//E2_ifdef verilator
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
   endfunction // get_mem
 
   // Function to write RAM (for use by Verilator).
   function set_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      input [data_width-1:0]             data;
      ram[addr] = data;
   endfunction // set_mem
//E2_endif
 
endmodule
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output reg [(data_width-1):0]          q_b;
   input                         clk_a, clk_b;
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
 
    generate
    if (memory_init == 1) begin : init_mem
        initial
            $readmemh(memory_file, ram);
    end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
    end
   endgenerate
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
 
    end
    endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
 
   always @ (posedge clk_b)
      q_b = ram[adr_b];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
 
    generate
    if (memory_init == 1) begin : init_mem
        initial
            $readmemh(memory_file, ram);
    end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
    end
   endgenerate
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
 
    end
    endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_1R2W
`define MODULE dpram_1r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
 
    generate
    if (memory_init == 1) begin : init_mem
        initial
            $readmemh(memory_file, ram);
    end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
    end
   endgenerate
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
        always @ (posedge clk_b)
        if (we_b)
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
    end
    endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
 
    generate
    if (memory_init) begin : init_mem
        initial
            $readmemh(memory_file, ram);
    end else if (memory_init == 2) begin : init_zero
        integer k;
        initial
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
    end
   endgenerate
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
        always @ (posedge clk_b)
        if (we_b)
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
    end
    endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter b_data_width = 64; //a_data_width;
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   localparam b_addr_width =
        (a_data_width==b_data_width) ? a_addr_width :
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
 
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter debug = 0;
 
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_data_width/8-1):0]    be_a;
   input                           we_a;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width-1):0]       d_b;
   input [(b_addr_width-1):0]       adr_b;
   input [(b_data_width/8-1):0]    be_b;
   input                           we_b;
   output reg [(b_data_width-1):0]          q_b;
   input                           clk_a, clk_b;
 
    generate
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        if (we_a)
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
        always @ (posedge clk_b)
        if (we_b)
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
    end
    endgenerate
 
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    initial
        if (memory_init==1)
            $readmemh(memory_file, ram);
 
    integer k;
    initial
        if (memory_init==2)
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
 
    always_ff@(posedge clk_a)
    begin
        if(we_a) begin
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
        end
    end
 
    always@(posedge clk_a)
        q_a = ram[adr_a];
 
    always_ff@(posedge clk_b)
    begin
        if(we_b) begin
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
        end
    end
 
    always@(posedge clk_b)
        q_b = ram[adr_b];
 
end
endgenerate
 
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
 
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
 
    initial
        if (memory_init==1)
            $readmemh(memory_file, ram);
 
    integer k;
    initial
        if (memory_init==2)
            for (k = 0; k < mem_size; k = k + 1)
                ram[k] = 0;
 
    always_ff@(posedge clk_a)
    begin
        if(we_a) begin
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
        end
    end
 
    always@(posedge clk_a)
        q_a = ram[adr_a];
 
    always_ff@(posedge clk_b)
    begin
        if(we_b) begin
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
        end
    end
 
    always@(posedge clk_b)
        q_b = ram[adr_b];
 
end
endgenerate
 
generate
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
logic [31:0] temp;
`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
dpram3232 (
    .d_a(d_a),
    .q_a(q_a),
    .adr_a(adr_a),
    .be_a(be_a),
    .we_a(we_a),
    .clk_a(clk_a),
    .d_b({d_b,d_b}),
    .q_b(temp),
    .adr_b(adr_b[b_addr_width-1:1]),
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
    .we_b(we_b),
    .clk_b(clk_b)
);
 
always @ (adr_b[0] or temp)
    if (adr_b[0])
        q_b = temp[31:16];
    else
        q_b = temp[15:0];
 
end
endgenerate
 
generate
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
logic [63:0] temp;
`define MODULE dpram_be_2r2w
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
dpram6464 (
    .d_a({d_a,d_a}),
    .q_a(temp),
    .adr_a(adr_a[a_addr_width-1:1]),
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
    .we_a(we_a),
    .clk_a(clk_a),
    .d_b(d_b),
    .q_b(q_b),
    .adr_b(adr_b),
    .be_b(be_b),
    .we_b(we_b),
    .clk_b(clk_b)
);
 
always @ (adr_a[0] or temp)
    if (adr_a[0])
        q_a = temp[63:32];
    else
        q_a = temp[31:0];
 
end
endgenerate
 
//E2_else
    // This modules requires SystemVerilog
    // at this point anyway
//E2_endif
endmodule
`endif
 
`ifdef CAM
// Content addresable memory, CAM
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef REG_FILE
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
parameter dw = 32;
parameter aw = 5;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input we3;
output [dw-1:0] rd1, rd2;
input clk, rst;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg sel1, sel2;
 
generate
if (debug==1) begin : debug_we
    always @ (posedge clk)
        if (we3)
            $display ("Value %h written at register %h : time %t", wd3, a3, $time);
end
endgenerate
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # ( .data_width(dw), .addr_width(aw))
    ram1 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd1mem),
        .adr_b(a1),
        .clk_b(clk) );
 
`BASE`MODULE
    # ( .data_width(dw), .addr_width(aw))
    ram2 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd2mem),
        .adr_b(a2),
        .clk_b(clk) );
`undef MODULE
 
always @ (posedge clk or posedge rst)
if (rst)
    {sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
else
    {sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51	75	unneback	`parameter mem_size = 1<<addr_width;`
52	7	unneback	`input [(addr_width-1):0] adr;`
53			`output reg [(data_width-1):0] q;`
54			`input clk;`
55	75	unneback	`reg [data_width-1:0] rom [mem_size-1:0];`
56	7	unneback	`parameter memory_file = "vl_rom.vmem";`
57			`initial`
58			`begin`
59			`$readmemh(memory_file, rom);`
60			`end`
61
62			`always @ (posedge clk)`
63			`q <= rom[adr];`
64	5	unneback
65	7	unneback	`endmodule`
66	40	unneback	`endif
67	7	unneback
68	40	unneback	`ifdef RAM
69			`define MODULE ram
70	5	unneback	`// Single port RAM`
71	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
72			`undef MODULE
73	5	unneback
74			`parameter data_width = 32;`
75			`parameter addr_width = 8;`
76	75	unneback	`parameter mem_size = 1<<addr_width;`
77	100	unneback	`parameter debug = 0;`
78	5	unneback	`input [(data_width-1):0] d;`
79			`input [(addr_width-1):0] adr;`
80			`input we;`
81	7	unneback	`output reg [(data_width-1):0] q;`
82	5	unneback	`input clk;`
83	98	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
84	100	unneback
85			`parameter memory_init = 0;`
86			`parameter memory_file = "vl_ram.vmem";`
87			`generate`
88			`if (memory_init == 1) begin : init_mem`
89			`initial`
90			`$readmemh(memory_file, ram);`
91			`end else if (memory_init == 2) begin : init_zero`
92			`integer k;`
93			`initial`
94			`for (k = 0; k < mem_size; k = k + 1)`
95			`ram[k] = 0;`
96	7	unneback	`end`
97			`endgenerate`
98
99	100	unneback	`generate`
100			`if (debug==1) begin : debug_we`
101			`always @ (posedge clk)`
102			`if (we)`
103			`$display ("Value %h written at address %h : time %t", d, adr, $time);`
104
105			`end`
106			`endgenerate`
107
108	5	unneback	`always @ (posedge clk)`
109			`begin`
110			`if (we)`
111			`ram[adr] <= d;`
112			`q <= ram[adr];`
113			`end`
114
115			`endmodule`
116	40	unneback	`endif
117	5	unneback
118	40	unneback	`ifdef RAM_BE
119			`define MODULE ram_be
120	91	unneback	module `BASE`MODULE ( d, adr, be, we, q, clk);
121	40	unneback	`undef MODULE
122
123	7	unneback	`parameter data_width = 32;`
124	72	unneback	`parameter addr_width = 6;`
125	75	unneback	`parameter mem_size = 1<<addr_width;`
126	7	unneback	`input [(data_width-1):0] d;`
127			`input [(addr_width-1):0] adr;`
128	73	unneback	`input [(data_width/8)-1:0] be;`
129	7	unneback	`input we;`
130			`output reg [(data_width-1):0] q;`
131			`input clk;`
132
133	84	unneback
134	65	unneback	`//E2_ifdef SYSTEMVERILOG`
135	95	unneback	`// use a multi-dimensional packed array`
136			`//t o model individual bytes within the word`
137			`logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width`
138	65	unneback	`//E2_else`
139	84	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
140			`wire [data_width/8-1:0] cke;`
141	65	unneback	`//E2_endif`
142
143	100	unneback	`parameter memory_init = 0;`
144			`parameter memory_file = "vl_ram.vmem";`
145			`generate`
146			`if (memory_init == 1) begin : init_mem`
147			`initial`
148			`$readmemh(memory_file, ram);`
149			`end else if (memory_init == 2) begin : init_zero`
150			`integer k;`
151			`initial`
152			`for (k = 0; k < mem_size; k = k + 1)`
153			`ram[k] = 0;`
154			`end`
155	7	unneback	`endgenerate`
156
157	60	unneback	`//E2_ifdef SYSTEMVERILOG`
158
159			`always_ff@(posedge clk)`
160			`begin`
161	95	unneback	`if(we) begin`
162	86	unneback	`if(be[3]) ram[adr][3] <= d[31:24];`
163			`if(be[2]) ram[adr][2] <= d[23:16];`
164			`if(be[1]) ram[adr][1] <= d[15:8];`
165			`if(be[0]) ram[adr][0] <= d[7:0];`
166	60	unneback	`end`
167	90	unneback	`q <= ram[adr];`
168	60	unneback	`end`
169
170			`//E2_else`
171
172	84	unneback	`assign cke = {data_width/8{we}} & be;`
173	7	unneback	`genvar i;`
174	84	unneback	`generate for (i=0;i<data_width/8;i=i+1) begin : be_ram`
175	7	unneback	`always @ (posedge clk)`
176	84	unneback	`if (cke[i])`
177	7	unneback	`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
178			`end`
179			`endgenerate`
180
181			`always @ (posedge clk)`
182			`q <= ram[adr];`
183
184	60	unneback	`//E2_endif`
185
186	93	unneback	`//E2_ifdef verilator`
187	84	unneback	`// Function to access RAM (for use by Verilator).`
188			`function [31:0] get_mem;`
189			`// verilator public`
190	90	unneback	`input [addr_width-1:0] addr;`
191	84	unneback	`get_mem = ram[addr];`
192			`endfunction // get_mem`
193
194			`// Function to write RAM (for use by Verilator).`
195			`function set_mem;`
196			`// verilator public`
197	90	unneback	`input [addr_width-1:0] addr;`
198			`input [data_width-1:0] data;`
199	84	unneback	`ram[addr] = data;`
200			`endfunction // set_mem`
201	93	unneback	`//E2_endif`
202	84	unneback
203	7	unneback	`endmodule`
204	40	unneback	`endif
205	7	unneback
206	40	unneback	`ifdef DPRAM_1R1W
207			`define MODULE dpram_1r1w
208			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
209			`undef MODULE
210	5	unneback	`parameter data_width = 32;`
211			`parameter addr_width = 8;`
212	75	unneback	`parameter mem_size = 1<<addr_width;`
213	5	unneback	`input [(data_width-1):0] d_a;`
214			`input [(addr_width-1):0] adr_a;`
215			`input [(addr_width-1):0] adr_b;`
216			`input we_a;`
217	118	unneback	`output reg [(data_width-1):0] q_b;`
218	5	unneback	`input clk_a, clk_b;`
219	119	unneback	reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
220	7	unneback
221	100	unneback	`parameter memory_init = 0;`
222			`parameter memory_file = "vl_ram.vmem";`
223			`parameter debug = 0;`
224
225			`generate`
226			`if (memory_init == 1) begin : init_mem`
227			`initial`
228			`$readmemh(memory_file, ram);`
229			`end else if (memory_init == 2) begin : init_zero`
230			`integer k;`
231			`initial`
232			`for (k = 0; k < mem_size; k = k + 1)`
233			`ram[k] = 0;`
234			`end`
235	7	unneback	`endgenerate`
236
237	100	unneback	`generate`
238			`if (debug==1) begin : debug_we`
239			`always @ (posedge clk_a)`
240			`if (we_a)`
241			`$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);`
242
243			`end`
244			`endgenerate`
245
246	5	unneback	`always @ (posedge clk_a)`
247			`if (we_a)`
248			`ram[adr_a] <= d_a;`
249	118	unneback
250	5	unneback	`always @ (posedge clk_b)`
251	118	unneback	`q_b = ram[adr_b];`
252	40	unneback
253	5	unneback	`endmodule`
254	40	unneback	`endif
255	5	unneback
256	40	unneback	`ifdef DPRAM_2R1W
257			`define MODULE dpram_2r1w
258			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
259			`undef MODULE
260
261	5	unneback	`parameter data_width = 32;`
262			`parameter addr_width = 8;`
263	75	unneback	`parameter mem_size = 1<<addr_width;`
264	5	unneback	`input [(data_width-1):0] d_a;`
265			`input [(addr_width-1):0] adr_a;`
266			`input [(addr_width-1):0] adr_b;`
267			`input we_a;`
268			`output [(data_width-1):0] q_b;`
269			`output reg [(data_width-1):0] q_a;`
270			`input clk_a, clk_b;`
271			`reg [(data_width-1):0] q_b;`
272	119	unneback	reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
273	7	unneback
274	100	unneback	`parameter memory_init = 0;`
275			`parameter memory_file = "vl_ram.vmem";`
276			`parameter debug = 0;`
277
278			`generate`
279			`if (memory_init == 1) begin : init_mem`
280			`initial`
281			`$readmemh(memory_file, ram);`
282			`end else if (memory_init == 2) begin : init_zero`
283			`integer k;`
284			`initial`
285			`for (k = 0; k < mem_size; k = k + 1)`
286			`ram[k] = 0;`
287			`end`
288	7	unneback	`endgenerate`
289
290	100	unneback	`generate`
291			`if (debug==1) begin : debug_we`
292			`always @ (posedge clk_a)`
293			`if (we_a)`
294			`$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);`
295
296			`end`
297			`endgenerate`
298
299	5	unneback	`always @ (posedge clk_a)`
300			`begin`
301			`q_a <= ram[adr_a];`
302			`if (we_a)`
303			`ram[adr_a] <= d_a;`
304			`end`
305			`always @ (posedge clk_b)`
306			`q_b <= ram[adr_b];`
307			`endmodule`
308	40	unneback	`endif
309	5	unneback
310	100	unneback	`ifdef DPRAM_1R2W
311			`define MODULE dpram_1r2w
312			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
313			`undef MODULE
314
315			`parameter data_width = 32;`
316			`parameter addr_width = 8;`
317			`parameter mem_size = 1<<addr_width;`
318			`input [(data_width-1):0] d_a;`
319			`input [(addr_width-1):0] adr_a;`
320			`input [(addr_width-1):0] adr_b;`
321			`input we_a;`
322			`input [(data_width-1):0] d_b;`
323			`output reg [(data_width-1):0] q_a;`
324			`input we_b;`
325			`input clk_a, clk_b;`
326			`reg [(data_width-1):0] q_b;`
327	119	unneback	reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
328	100	unneback
329			`parameter memory_init = 0;`
330			`parameter memory_file = "vl_ram.vmem";`
331			`parameter debug = 0;`
332
333			`generate`
334			`if (memory_init == 1) begin : init_mem`
335			`initial`
336			`$readmemh(memory_file, ram);`
337			`end else if (memory_init == 2) begin : init_zero`
338			`integer k;`
339			`initial`
340			`for (k = 0; k < mem_size; k = k + 1)`
341			`ram[k] = 0;`
342			`end`
343			`endgenerate`
344
345			`generate`
346			`if (debug==1) begin : debug_we`
347			`always @ (posedge clk_a)`
348			`if (we_a)`
349			`$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);`
350			`always @ (posedge clk_b)`
351			`if (we_b)`
352			`$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);`
353			`end`
354			`endgenerate`
355
356			`always @ (posedge clk_a)`
357			`begin`
358			`q_a <= ram[adr_a];`
359			`if (we_a)`
360			`ram[adr_a] <= d_a;`
361			`end`
362			`always @ (posedge clk_b)`
363			`begin`
364			`if (we_b)`
365			`ram[adr_b] <= d_b;`
366			`end`
367			`endmodule`
368			`endif
369
370	40	unneback	`ifdef DPRAM_2R2W
371			`define MODULE dpram_2r2w
372			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
373			`undef MODULE
374
375	5	unneback	`parameter data_width = 32;`
376			`parameter addr_width = 8;`
377	75	unneback	`parameter mem_size = 1<<addr_width;`
378	5	unneback	`input [(data_width-1):0] d_a;`
379			`input [(addr_width-1):0] adr_a;`
380			`input [(addr_width-1):0] adr_b;`
381			`input we_a;`
382			`output [(data_width-1):0] q_b;`
383			`input [(data_width-1):0] d_b;`
384			`output reg [(data_width-1):0] q_a;`
385			`input we_b;`
386			`input clk_a, clk_b;`
387			`reg [(data_width-1):0] q_b;`
388	119	unneback	reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
389	7	unneback
390	100	unneback	`parameter memory_init = 0;`
391			`parameter memory_file = "vl_ram.vmem";`
392			`parameter debug = 0;`
393
394			`generate`
395			`if (memory_init) begin : init_mem`
396			`initial`
397			`$readmemh(memory_file, ram);`
398			`end else if (memory_init == 2) begin : init_zero`
399			`integer k;`
400			`initial`
401			`for (k = 0; k < mem_size; k = k + 1)`
402			`ram[k] = 0;`
403			`end`
404	7	unneback	`endgenerate`
405
406	100	unneback	`generate`
407			`if (debug==1) begin : debug_we`
408			`always @ (posedge clk_a)`
409			`if (we_a)`
410			`$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);`
411			`always @ (posedge clk_b)`
412			`if (we_b)`
413			`$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);`
414			`end`
415			`endgenerate`
416
417	5	unneback	`always @ (posedge clk_a)`
418			`begin`
419			`q_a <= ram[adr_a];`
420			`if (we_a)`
421			`ram[adr_a] <= d_a;`
422			`end`
423			`always @ (posedge clk_b)`
424			`begin`
425			`q_b <= ram[adr_b];`
426			`if (we_b)`
427			`ram[adr_b] <= d_b;`
428			`end`
429			`endmodule`
430	40	unneback	`endif
431	5	unneback
432	83	unneback
433	75	unneback	`ifdef DPRAM_BE_2R2W
434			`define MODULE dpram_be_2r2w
435	92	unneback	module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
436	75	unneback	`undef MODULE
437
438			`parameter a_data_width = 32;`
439			`parameter a_addr_width = 8;`
440	95	unneback	`parameter b_data_width = 64; //a_data_width;`
441	124	unneback	`//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;`
442			`localparam b_addr_width =`
443	125	unneback	`(a_data_width==b_data_width) ? a_addr_width :`
444			`(a_data_width==b_data_width*2) ? a_addr_width+1 :`
445			`(a_data_width==b_data_width*4) ? a_addr_width+2 :`
446			`(a_data_width==b_data_width*8) ? a_addr_width+3 :`
447			`(a_data_width==b_data_width*16) ? a_addr_width+4 :`
448			`(a_data_width==b_data_width*32) ? a_addr_width+5 :`
449			`(a_data_width==b_data_width/2) ? a_addr_width-1 :`
450			`(a_data_width==b_data_width/4) ? a_addr_width-2 :`
451			`(a_data_width==b_data_width/8) ? a_addr_width-3 :`
452			`(a_data_width==b_data_width/16) ? a_addr_width-4 :`
453			`(a_data_width==b_data_width/32) ? a_addr_width-5 : 0;`
454	124	unneback
455	95	unneback	`localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);`
456			`parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);`
457	91	unneback
458	100	unneback	`parameter memory_init = 0;`
459	95	unneback	`parameter memory_file = "vl_ram.vmem";`
460	100	unneback	`parameter debug = 0;`
461	95	unneback
462	75	unneback	`input [(a_data_width-1):0] d_a;`
463	91	unneback	`input [(a_addr_width-1):0] adr_a;`
464			`input [(a_data_width/8-1):0] be_a;`
465			`input we_a;`
466	75	unneback	`output reg [(a_data_width-1):0] q_a;`
467	91	unneback	`input [(b_data_width-1):0] d_b;`
468			`input [(b_addr_width-1):0] adr_b;`
469	92	unneback	`input [(b_data_width/8-1):0] be_b;`
470			`input we_b;`
471			`output reg [(b_data_width-1):0] q_b;`
472	91	unneback	`input clk_a, clk_b;`
473	75	unneback
474	100	unneback	`generate`
475			`if (debug==1) begin : debug_we`
476			`always @ (posedge clk_a)`
477			`if (we_a)`
478	141	unneback	`$display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);`
479	100	unneback	`always @ (posedge clk_b)`
480			`if (we_b)`
481	141	unneback	`$display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);`
482	100	unneback	`end`
483			`endgenerate`
484
485
486	91	unneback	`//E2_ifdef SYSTEMVERILOG`
487			`// use a multi-dimensional packed array`
488			`//to model individual bytes within the word`
489
490	75	unneback	`generate`
491	91	unneback	`if (a_data_width==32 & b_data_width==32) begin : dpram_3232`
492	75	unneback
493	98	unneback	logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
494	95	unneback
495			`initial`
496	100	unneback	`if (memory_init==1)`
497	95	unneback	`$readmemh(memory_file, ram);`
498	100	unneback
499			`integer k;`
500			`initial`

Browse

Tools

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Blame information for rev 148