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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
/// ROM
 
module vl_rom_init ( adr, q, clk);
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
 
/*
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
    {32'h18000000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'h44003000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000}};
 
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
    q <= data[adr];
 
endmodule
*/
// Single port RAM
 
module vl_ram ( d, adr, we, q, clk);
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width/4)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
endmodule
 
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
`ifdef ACTEL
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
endmodule
 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
 
// Content addresable memory, CAM
 
// FIFO
 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
 
endmodule // async_comp
 
module vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dpram_1r1w
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
vl_fifo_cmp_async
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
 
endmodule
 
module vl_fifo_2r2w_async (
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
 
endmodule
 
module vl_fifo_2r2w_async_simplex (
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vl_dpram_2r2w
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
 
vl_fifo_cmp_async
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
vl_fifo_cmp_async
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
endmodule

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43			`/// ROM`
44
45	7	unneback	`module vl_rom_init ( adr, q, clk);`
46			`parameter data_width = 32;`
47			`parameter addr_width = 8;`
48			`input [(addr_width-1):0] adr;`
49			`output reg [(data_width-1):0] q;`
50			`input clk;`
51			`reg [data_width-1:0] rom [(1<<addr_width)-1:0];`
52			`parameter memory_file = "vl_rom.vmem";`
53			`initial`
54			`begin`
55			`$readmemh(memory_file, rom);`
56			`end`
57
58			`always @ (posedge clk)`
59			`q <= rom[adr];`
60	5	unneback
61	7	unneback	`endmodule`
62
63	14	unneback	`/*`
64	7	unneback	`module vl_rom ( adr, q, clk);`
65
66	5	unneback	`parameter data_width = 32;`
67			`parameter addr_width = 4;`
68
69			`parameter [0:1>>addr_width-1] data [data_width-1:0] = {`
70			`{32'h18000000},`
71			`{32'hA8200000},`
72			`{32'hA8200000},`
73			`{32'hA8200000},`
74			`{32'h44003000},`
75			`{32'h15000000},`
76			`{32'h15000000},`
77			`{32'h15000000},`
78			`{32'h15000000},`
79			`{32'h15000000},`
80			`{32'h15000000},`
81			`{32'h15000000},`
82			`{32'h15000000},`
83			`{32'h15000000},`
84			`{32'h15000000},`
85			`{32'h15000000}};`
86
87	7	unneback	`input [addr_width-1:0] adr;`
88	5	unneback	`output reg [data_width-1:0] q;`
89			`input clk;`
90
91			`always @ (posedge clk)`
92	7	unneback	`q <= data[adr];`
93	5	unneback
94			`endmodule`
95	14	unneback	`*/`
96	5	unneback	`// Single port RAM`
97
98			`module vl_ram ( d, adr, we, q, clk);`
99			`parameter data_width = 32;`
100			`parameter addr_width = 8;`
101			`input [(data_width-1):0] d;`
102			`input [(addr_width-1):0] adr;`
103			`input we;`
104	7	unneback	`output reg [(data_width-1):0] q;`
105	5	unneback	`input clk;`
106			`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`
107	7	unneback	`parameter init = 0;`
108			`parameter memory_file = "vl_ram.vmem";`
109			`generate if (init) begin : init_mem`
110			`initial`
111			`begin`
112			`$readmemh(memory_file, ram);`
113			`end`
114			`end`
115			`endgenerate`
116
117	5	unneback	`always @ (posedge clk)`
118			`begin`
119			`if (we)`
120			`ram[adr] <= d;`
121			`q <= ram[adr];`
122			`end`
123
124			`endmodule`
125
126	7	unneback	`module vl_ram_be ( d, adr, be, we, q, clk);`
127			`parameter data_width = 32;`
128			`parameter addr_width = 8;`
129			`input [(data_width-1):0] d;`
130			`input [(addr_width-1):0] adr;`
131			`input [(addr_width/4)-1:0] be;`
132			`input we;`
133			`output reg [(data_width-1):0] q;`
134			`input clk;`
135
136			`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`
137
138			`parameter init = 0;`
139			`parameter memory_file = "vl_ram.vmem";`
140			`generate if (init) begin : init_mem`
141			`initial`
142			`begin`
143			`$readmemh(memory_file, ram);`
144			`end`
145			`end`
146			`endgenerate`
147
148			`genvar i;`
149			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram`
150			`always @ (posedge clk)`
151			`if (we & be[i])`
152			`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
153			`end`
154			`endgenerate`
155
156			`always @ (posedge clk)`
157			`q <= ram[adr];`
158
159			`endmodule`
160
161
162	5	unneback	`// Dual port RAM`
163
164			`// ACTEL FPGA should not use logic to handle rw collision`
165			`ifdef ACTEL
166			`define SYN /synthesis syn_ramstyle = "no_rw_check"/
167			`else
168			`define SYN
169			`endif
170
171	7	unneback	`module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );`
172	5	unneback	`parameter data_width = 32;`
173			`parameter addr_width = 8;`
174			`input [(data_width-1):0] d_a;`
175			`input [(addr_width-1):0] adr_a;`
176			`input [(addr_width-1):0] adr_b;`
177			`input we_a;`
178			`output [(data_width-1):0] q_b;`
179			`input clk_a, clk_b;`
180			`reg [(addr_width-1):0] adr_b_reg;`
181			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
182	7	unneback
183			`parameter init = 0;`
184			`parameter memory_file = "vl_ram.vmem";`
185			`generate if (init) begin : init_mem`
186			`initial`
187			`begin`
188			`$readmemh(memory_file, ram);`
189			`end`
190			`end`
191			`endgenerate`
192
193	5	unneback	`always @ (posedge clk_a)`
194			`if (we_a)`
195			`ram[adr_a] <= d_a;`
196			`always @ (posedge clk_b)`
197			`adr_b_reg <= adr_b;`
198			`assign q_b = ram[adr_b_reg];`
199			`endmodule`
200
201	7	unneback	`module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );`
202	5	unneback	`parameter data_width = 32;`
203			`parameter addr_width = 8;`
204			`input [(data_width-1):0] d_a;`
205			`input [(addr_width-1):0] adr_a;`
206			`input [(addr_width-1):0] adr_b;`
207			`input we_a;`
208			`output [(data_width-1):0] q_b;`
209			`output reg [(data_width-1):0] q_a;`
210			`input clk_a, clk_b;`
211			`reg [(data_width-1):0] q_b;`
212			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
213	7	unneback
214			`parameter init = 0;`
215			`parameter memory_file = "vl_ram.vmem";`
216			`generate if (init) begin : init_mem`
217			`initial`
218			`begin`
219			`$readmemh(memory_file, ram);`
220			`end`
221			`end`
222			`endgenerate`
223
224	5	unneback	`always @ (posedge clk_a)`
225			`begin`
226			`q_a <= ram[adr_a];`
227			`if (we_a)`
228			`ram[adr_a] <= d_a;`
229			`end`
230			`always @ (posedge clk_b)`
231			`q_b <= ram[adr_b];`
232			`endmodule`
233
234	7	unneback	`module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );`
235	5	unneback	`parameter data_width = 32;`
236			`parameter addr_width = 8;`
237			`input [(data_width-1):0] d_a;`
238			`input [(addr_width-1):0] adr_a;`
239			`input [(addr_width-1):0] adr_b;`
240			`input we_a;`
241			`output [(data_width-1):0] q_b;`
242			`input [(data_width-1):0] d_b;`
243			`output reg [(data_width-1):0] q_a;`
244			`input we_b;`
245			`input clk_a, clk_b;`
246			`reg [(data_width-1):0] q_b;`
247			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
248	7	unneback
249			`parameter init = 0;`
250			`parameter memory_file = "vl_ram.vmem";`
251			`generate if (init) begin : init_mem`
252			`initial`
253			`begin`
254			`$readmemh(memory_file, ram);`
255			`end`
256			`end`
257			`endgenerate`
258
259	5	unneback	`always @ (posedge clk_a)`
260			`begin`
261			`q_a <= ram[adr_a];`
262			`if (we_a)`
263			`ram[adr_a] <= d_a;`
264			`end`
265			`always @ (posedge clk_b)`
266			`begin`
267			`q_b <= ram[adr_b];`
268			`if (we_b)`
269			`ram[adr_b] <= d_b;`
270			`end`
271			`endmodule`
272
273			`// Content addresable memory, CAM`
274
275			`// FIFO`
276
277			`module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );`
278
279	11	unneback	`parameter addr_width = 4;`
280			`parameter N = addr_width-1;`
281	5	unneback
282			`parameter Q1 = 2'b00;`
283			`parameter Q2 = 2'b01;`
284			`parameter Q3 = 2'b11;`
285			`parameter Q4 = 2'b10;`
286
287			`parameter going_empty = 1'b0;`
288			`parameter going_full = 1'b1;`
289
290			`input [N:0] wptr, rptr;`
291	14	unneback	`output fifo_empty;`
292	5	unneback	`output fifo_full;`
293			`input wclk, rclk, rst;`
294
295			`ifndef GENERATE_DIRECTION_AS_LATCH
296			`wire direction;`
297			`endif
298			`ifdef GENERATE_DIRECTION_AS_LATCH
299			`reg direction;`
300			`endif
301			`reg direction_set, direction_clr;`
302
303			`wire async_empty, async_full;`
304			`wire fifo_full2;`
305	14	unneback	`wire fifo_empty2;`
306	5	unneback
307			`// direction_set`
308			`always @ (wptr[N:N-1] or rptr[N:N-1])`
309			`case ({wptr[N:N-1],rptr[N:N-1]})`
310			`{Q1,Q2} : direction_set <= 1'b1;`
311			`{Q2,Q3} : direction_set <= 1'b1;`
312			`{Q3,Q4} : direction_set <= 1'b1;`
313			`{Q4,Q1} : direction_set <= 1'b1;`
314			`default : direction_set <= 1'b0;`
315			`endcase`
316
317			`// direction_clear`
318			`always @ (wptr[N:N-1] or rptr[N:N-1] or rst)`
319			`if (rst)`
320			`direction_clr <= 1'b1;`
321			`else`
322			`case ({wptr[N:N-1],rptr[N:N-1]})`
323			`{Q2,Q1} : direction_clr <= 1'b1;`
324			`{Q3,Q2} : direction_clr <= 1'b1;`
325			`{Q4,Q3} : direction_clr <= 1'b1;`
326			`{Q1,Q4} : direction_clr <= 1'b1;`
327			`default : direction_clr <= 1'b0;`
328			`endcase`
329
330			`ifndef GENERATE_DIRECTION_AS_LATCH
331	18	unneback	`vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));`
332	5	unneback	`endif
333
334			`ifdef GENERATE_DIRECTION_AS_LATCH
335			`always @ (posedge direction_set or posedge direction_clr)`
336			`if (direction_clr)`
337			`direction <= going_empty;`
338			`else`
339			`direction <= going_full;`
340			`endif
341
342			`assign async_empty = (wptr == rptr) && (direction==going_empty);`
343			`assign async_full = (wptr == rptr) && (direction==going_full);`
344
345	18	unneback	`vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));`
346			`vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));`
347	5	unneback
348			`/*`
349			`always @ (posedge wclk or posedge rst or posedge async_full)`
350			`if (rst)`
351			`{fifo_full, fifo_full2} <= 2'b00;`
352			`else if (async_full)`
353			`{fifo_full, fifo_full2} <= 2'b11;`
354			`else`
355			`{fifo_full, fifo_full2} <= {fifo_full2, async_full};`
356			`*/`
357	14	unneback	`/* always @ (posedge rclk or posedge async_empty)`
358	5	unneback	`if (async_empty)`
359			`{fifo_empty, fifo_empty2} <= 2'b11;`
360			`else`
361	14	unneback	`{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */`
362	18	unneback	`vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));`
363			`vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));`
364	5	unneback
365			`endmodule // async_comp`
366
367			`module vl_fifo_1r1w_async (`
368			`d, wr, fifo_full, wr_clk, wr_rst,`
369			`q, rd, fifo_empty, rd_clk, rd_rst`
370			`);`
371
372			`parameter data_width = 18;`
373			`parameter addr_width = 4;`
374
375			`// write side`
376			`input [data_width-1:0] d;`
377			`input wr;`
378			`output fifo_full;`
379			`input wr_clk;`
380			`input wr_rst;`
381			`// read side`
382			`output [data_width-1:0] q;`
383			`input rd;`
384			`output fifo_empty;`
385			`input rd_clk;`
386			`input rd_rst;`
387
388			`wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;`
389
390			`vl_fifo_1r1w_async (`
391			`d, wr, fifo_full, wr_clk, wr_rst,`
392			`q, rd, fifo_empty, rd_clk, rd_rst`
393			`);`
394
395	18	unneback	`vl_cnt_gray_ce_bin`
396	5	unneback	`# ( .length(addr_width))`
397			`fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));`
398
399	18	unneback	`vl_cnt_gray_ce_bin`
400	5	unneback	`# (.length(addr_width))`
401			`fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));`
402
403	7	unneback	`vl_dpram_1r1w`
404	5	unneback	`# (.data_width(data_width), .addr_width(addr_width))`
405			`dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));`
406
407			`vl_fifo_cmp_async`
408			`# (.addr_width(addr_width))`
409			`cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );`
410
411			`endmodule`
412
413	7	unneback	`module vl_fifo_2r2w_async (`
414	5	unneback	`// a side`
415			`a_d, a_wr, a_fifo_full,`
416			`a_q, a_rd, a_fifo_empty,`
417			`a_clk, a_rst,`
418			`// b side`
419			`b_d, b_wr, b_fifo_full,`
420			`b_q, b_rd, b_fifo_empty,`
421			`b_clk, b_rst`
422			`);`
423
424			`parameter data_width = 18;`
425			`parameter addr_width = 4;`
426
427			`// a side`
428			`input [data_width-1:0] a_d;`
429			`input a_wr;`
430			`output a_fifo_full;`
431			`output [data_width-1:0] a_q;`
432			`input a_rd;`
433			`output a_fifo_empty;`
434			`input a_clk;`
435			`input a_rst;`
436
437			`// b side`
438			`input [data_width-1:0] b_d;`
439			`input b_wr;`
440			`output b_fifo_full;`
441			`output [data_width-1:0] b_q;`
442			`input b_rd;`
443			`output b_fifo_empty;`
444			`input b_clk;`
445			`input b_rst;`
446
447			`vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))`
448			`vl_fifo_1r1w_async_a (`
449			`.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),`
450			`.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)`
451			`);`
452
453			`vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))`
454			`vl_fifo_1r1w_async_b (`
455			`.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),`
456			`.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)`
457			`);`
458
459			`endmodule`
460
461	7	unneback	`module vl_fifo_2r2w_async_simplex (`
462	5	unneback	`// a side`
463			`a_d, a_wr, a_fifo_full,`
464			`a_q, a_rd, a_fifo_empty,`
465			`a_clk, a_rst,`
466			`// b side`
467			`b_d, b_wr, b_fifo_full,`
468			`b_q, b_rd, b_fifo_empty,`
469			`b_clk, b_rst`
470			`);`
471
472			`parameter data_width = 18;`
473			`parameter addr_width = 4;`
474
475			`// a side`
476			`input [data_width-1:0] a_d;`
477			`input a_wr;`
478			`output a_fifo_full;`
479			`output [data_width-1:0] a_q;`
480			`input a_rd;`
481			`output a_fifo_empty;`
482			`input a_clk;`
483			`input a_rst;`
484
485			`// b side`
486			`input [data_width-1:0] b_d;`
487			`input b_wr;`
488			`output b_fifo_full;`
489			`output [data_width-1:0] b_q;`
490			`input b_rd;`
491			`output b_fifo_empty;`
492			`input b_clk;`
493			`input b_rst;`
494
495			`// adr_gen`
496			`wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;`
497			`wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;`
498			`// dpram`
499			`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
500

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