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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
/*
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
    {32'h18000000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'h44003000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000}};
 
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
    q <= data[adr];
 
endmodule
*/
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width/4)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
endmodule
`endif
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
`ifdef ACTEL
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
// Content addresable memory, CAM
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51			`input [(addr_width-1):0] adr;`
52			`output reg [(data_width-1):0] q;`
53			`input clk;`
54			`reg [data_width-1:0] rom [(1<<addr_width)-1:0];`
55			`parameter memory_file = "vl_rom.vmem";`
56			`initial`
57			`begin`
58			`$readmemh(memory_file, rom);`
59			`end`
60
61			`always @ (posedge clk)`
62			`q <= rom[adr];`
63	5	unneback
64	7	unneback	`endmodule`
65	40	unneback	`endif
66	7	unneback
67	14	unneback	`/*`
68	7	unneback	`module vl_rom ( adr, q, clk);`
69
70	5	unneback	`parameter data_width = 32;`
71			`parameter addr_width = 4;`
72
73			`parameter [0:1>>addr_width-1] data [data_width-1:0] = {`
74			`{32'h18000000},`
75			`{32'hA8200000},`
76			`{32'hA8200000},`
77			`{32'hA8200000},`
78			`{32'h44003000},`
79			`{32'h15000000},`
80			`{32'h15000000},`
81			`{32'h15000000},`
82			`{32'h15000000},`
83			`{32'h15000000},`
84			`{32'h15000000},`
85			`{32'h15000000},`
86			`{32'h15000000},`
87			`{32'h15000000},`
88			`{32'h15000000},`
89			`{32'h15000000}};`
90
91	7	unneback	`input [addr_width-1:0] adr;`
92	5	unneback	`output reg [data_width-1:0] q;`
93			`input clk;`
94
95			`always @ (posedge clk)`
96	7	unneback	`q <= data[adr];`
97	5	unneback
98			`endmodule`
99	14	unneback	`*/`
100	40	unneback
101			`ifdef RAM
102			`define MODULE ram
103	5	unneback	`// Single port RAM`
104	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
105			`undef MODULE
106	5	unneback
107			`parameter data_width = 32;`
108			`parameter addr_width = 8;`
109			`input [(data_width-1):0] d;`
110			`input [(addr_width-1):0] adr;`
111			`input we;`
112	7	unneback	`output reg [(data_width-1):0] q;`
113	5	unneback	`input clk;`
114			`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`
115	7	unneback	`parameter init = 0;`
116			`parameter memory_file = "vl_ram.vmem";`
117			`generate if (init) begin : init_mem`
118			`initial`
119			`begin`
120			`$readmemh(memory_file, ram);`
121			`end`
122			`end`
123			`endgenerate`
124
125	5	unneback	`always @ (posedge clk)`
126			`begin`
127			`if (we)`
128			`ram[adr] <= d;`
129			`q <= ram[adr];`
130			`end`
131
132			`endmodule`
133	40	unneback	`endif
134	5	unneback
135	40	unneback	`ifdef RAM_BE
136			`define MODULE ram_be
137			module `BASE`MODULE ( d, adr, be, we, q, clk);
138			`undef MODULE
139
140	7	unneback	`parameter data_width = 32;`
141			`parameter addr_width = 8;`
142			`input [(data_width-1):0] d;`
143			`input [(addr_width-1):0] adr;`
144			`input [(addr_width/4)-1:0] be;`
145			`input we;`
146			`output reg [(data_width-1):0] q;`
147			`input clk;`
148
149			`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`
150
151			`parameter init = 0;`
152			`parameter memory_file = "vl_ram.vmem";`
153			`generate if (init) begin : init_mem`
154			`initial`
155			`begin`
156			`$readmemh(memory_file, ram);`
157			`end`
158			`end`
159			`endgenerate`
160
161			`genvar i;`
162			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram`
163			`always @ (posedge clk)`
164			`if (we & be[i])`
165			`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
166			`end`
167			`endgenerate`
168
169			`always @ (posedge clk)`
170			`q <= ram[adr];`
171
172			`endmodule`
173	40	unneback	`endif
174	7	unneback
175	5	unneback	`// Dual port RAM`
176
177			`// ACTEL FPGA should not use logic to handle rw collision`
178			`ifdef ACTEL
179			`define SYN /synthesis syn_ramstyle = "no_rw_check"/
180			`else
181			`define SYN
182			`endif
183
184	40	unneback	`ifdef DPRAM_1R1W
185			`define MODULE dpram_1r1w
186			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
187			`undef MODULE
188	5	unneback	`parameter data_width = 32;`
189			`parameter addr_width = 8;`
190			`input [(data_width-1):0] d_a;`
191			`input [(addr_width-1):0] adr_a;`
192			`input [(addr_width-1):0] adr_b;`
193			`input we_a;`
194			`output [(data_width-1):0] q_b;`
195			`input clk_a, clk_b;`
196			`reg [(addr_width-1):0] adr_b_reg;`
197			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
198	7	unneback
199			`parameter init = 0;`
200			`parameter memory_file = "vl_ram.vmem";`
201			`generate if (init) begin : init_mem`
202			`initial`
203			`begin`
204			`$readmemh(memory_file, ram);`
205			`end`
206			`end`
207			`endgenerate`
208
209	5	unneback	`always @ (posedge clk_a)`
210			`if (we_a)`
211			`ram[adr_a] <= d_a;`
212			`always @ (posedge clk_b)`
213			`adr_b_reg <= adr_b;`
214			`assign q_b = ram[adr_b_reg];`
215	40	unneback
216	5	unneback	`endmodule`
217	40	unneback	`endif
218	5	unneback
219	40	unneback	`ifdef DPRAM_2R1W
220			`define MODULE dpram_2r1w
221			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
222			`undef MODULE
223
224	5	unneback	`parameter data_width = 32;`
225			`parameter addr_width = 8;`
226			`input [(data_width-1):0] d_a;`
227			`input [(addr_width-1):0] adr_a;`
228			`input [(addr_width-1):0] adr_b;`
229			`input we_a;`
230			`output [(data_width-1):0] q_b;`
231			`output reg [(data_width-1):0] q_a;`
232			`input clk_a, clk_b;`
233			`reg [(data_width-1):0] q_b;`
234			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
235	7	unneback
236			`parameter init = 0;`
237			`parameter memory_file = "vl_ram.vmem";`
238			`generate if (init) begin : init_mem`
239			`initial`
240			`begin`
241			`$readmemh(memory_file, ram);`
242			`end`
243			`end`
244			`endgenerate`
245
246	5	unneback	`always @ (posedge clk_a)`
247			`begin`
248			`q_a <= ram[adr_a];`
249			`if (we_a)`
250			`ram[adr_a] <= d_a;`
251			`end`
252			`always @ (posedge clk_b)`
253			`q_b <= ram[adr_b];`
254			`endmodule`
255	40	unneback	`endif
256	5	unneback
257	40	unneback	`ifdef DPRAM_2R2W
258			`define MODULE dpram_2r2w
259			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
260			`undef MODULE
261
262	5	unneback	`parameter data_width = 32;`
263			`parameter addr_width = 8;`
264			`input [(data_width-1):0] d_a;`
265			`input [(addr_width-1):0] adr_a;`
266			`input [(addr_width-1):0] adr_b;`
267			`input we_a;`
268			`output [(data_width-1):0] q_b;`
269			`input [(data_width-1):0] d_b;`
270			`output reg [(data_width-1):0] q_a;`
271			`input we_b;`
272			`input clk_a, clk_b;`
273			`reg [(data_width-1):0] q_b;`
274			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
275	7	unneback
276			`parameter init = 0;`
277			`parameter memory_file = "vl_ram.vmem";`
278			`generate if (init) begin : init_mem`
279			`initial`
280			`begin`
281			`$readmemh(memory_file, ram);`
282			`end`
283			`end`
284			`endgenerate`
285
286	5	unneback	`always @ (posedge clk_a)`
287			`begin`
288			`q_a <= ram[adr_a];`
289			`if (we_a)`
290			`ram[adr_a] <= d_a;`
291			`end`
292			`always @ (posedge clk_b)`
293			`begin`
294			`q_b <= ram[adr_b];`
295			`if (we_b)`
296			`ram[adr_b] <= d_b;`
297			`end`
298			`endmodule`
299	40	unneback	`endif
300	5	unneback
301			`// Content addresable memory, CAM`
302
303	40	unneback	`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
304	5	unneback	`// FIFO`
305	40	unneback	`define MODULE fifo_1r1w_fill_level_sync
306			module `BASE`MODULE (
307			`undef MODULE
308	25	unneback	`d, wr, fifo_full,`
309			`q, rd, fifo_empty,`
310			`fill_level,`
311			`clk, rst`
312			`);`
313
314			`parameter data_width = 18;`
315			`parameter addr_width = 4;`
316	5	unneback
317	25	unneback	`// write side`
318			`input [data_width-1:0] d;`
319			`input wr;`
320			`output fifo_full;`
321			`// read side`
322			`output [data_width-1:0] q;`
323			`input rd;`
324			`output fifo_empty;`
325			`// common`
326			`output [addr_width:0] fill_level;`
327			`input rst, clk;`
328
329			`wire [addr_width:1] wadr, radr;`
330
331	40	unneback	`define MODULE cnt_bin_ce
332			`BASE`MODULE
333	25	unneback	`# ( .length(addr_width))`
334			`fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));`
335	40	unneback	`BASE`MODULE
336	25	unneback	`# (.length(addr_width))`
337			`fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));`
338	40	unneback	`undef MODULE
339	25	unneback
340	40	unneback	`define MODULE dpram_1r1w
341			`BASE`MODULE
342	25	unneback	`# (.data_width(data_width), .addr_width(addr_width))`
343			`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`
344	40	unneback	`undef MODULE
345	25	unneback
346	40	unneback	`define MODULE cnt_bin_ce_rew_q_zq_l1
347			`BASE`MODULE
348	27	unneback	`# (.length(addr_width+1), .level1_value(1<<addr_width))`
349	25	unneback	`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`
350	40	unneback	`undef MODULE
351	25	unneback	`endmodule`
352	40	unneback	`endif
353	25	unneback
354	40	unneback	`ifdef FIFO_2R2W_SYNC_SIMPLEX
355	27	unneback	`// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource`
356			`// RAM is supposed to be larger than the two FIFOs`
357			`// LFSR counters used adr pointers`
358	40	unneback	`define MODULE fifo_2r2w_sync_simplex
359			module `BASE`MODULE (
360			`undef MODULE
361	27	unneback	`// a side`
362			`a_d, a_wr, a_fifo_full,`
363			`a_q, a_rd, a_fifo_empty,`
364			`a_fill_level,`
365			`// b side`
366			`b_d, b_wr, b_fifo_full,`
367			`b_q, b_rd, b_fifo_empty,`
368			`b_fill_level,`
369			`// common`
370			`clk, rst`
371			`);`
372			`parameter data_width = 8;`
373			`parameter addr_width = 5;`
374			`parameter fifo_full_level = (1<<addr_width)-1;`
375
376			`// a side`
377			`input [data_width-1:0] a_d;`
378			`input a_wr;`
379			`output a_fifo_full;`
380			`output [data_width-1:0] a_q;`
381			`input a_rd;`
382			`output a_fifo_empty;`
383			`output [addr_width-1:0] a_fill_level;`
384
385			`// b side`
386			`input [data_width-1:0] b_d;`
387			`input b_wr;`
388			`output b_fifo_full;`
389			`output [data_width-1:0] b_q;`
390			`input b_rd;`
391			`output b_fifo_empty;`
392			`output [addr_width-1:0] b_fill_level;`
393
394			`input clk;`
395			`input rst;`
396
397			`// adr_gen`
398			`wire [addr_width:1] a_wadr, a_radr;`
399			`wire [addr_width:1] b_wadr, b_radr;`
400			`// dpram`
401			`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
402
403	40	unneback	`define MODULE cnt_lfsr_ce
404			`BASE`MODULE
405	27	unneback	`# ( .length(addr_width))`
406			`fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));`
407
408	40	unneback	`BASE`MODULE
409	27	unneback	`# (.length(addr_width))`
410			`fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));`
411
412	40	unneback	`BASE`MODULE
413	27	unneback	`# ( .length(addr_width))`
414			`fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));`
415
416	40	unneback	`BASE`MODULE
417	27	unneback	`# (.length(addr_width))`
418			`fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));`
419	40	unneback	`undef MODULE
420	27	unneback
421			`// mux read or write adr to DPRAM`
422			`assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};`
423			`assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};`
424
425	40	unneback	`define MODULE dpram_2r2w
426			`BASE`MODULE
427	27	unneback	`# (.data_width(data_width), .addr_width(addr_width+1))`
428			`dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),`
429			`.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));`
430	40	unneback	`undef MODULE
431
432			`define MODULE cnt_bin_ce_rew_zq_l1
433			`BASE`MODULE
434	28	unneback	`# (.length(addr_width), .level1_value(fifo_full_level))`
435	27	unneback	`a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));`
436
437	40	unneback	`BASE`MODULE
438	28	unneback	`# (.length(addr_width), .level1_value(fifo_full_level))`
439	27	unneback	`b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));`
440	40	unneback	`undef MODULE
441	27	unneback
442			`endmodule`
443	40	unneback	`endif
444	27	unneback
445	40	unneback	`ifdef FIFO_CMP_ASYNC
446			`define MODULE fifo_cmp_async
447			module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
448			`undef MODULE
449	5	unneback
450	11	unneback	`parameter addr_width = 4;`
451			`parameter N = addr_width-1;`
452	5	unneback
453			`parameter Q1 = 2'b00;`
454			`parameter Q2 = 2'b01;`
455			`parameter Q3 = 2'b11;`
456			`parameter Q4 = 2'b10;`
457
458			`parameter going_empty = 1'b0;`
459			`parameter going_full = 1'b1;`
460
461			`input [N:0] wptr, rptr;`
462	14	unneback	`output fifo_empty;`
463	5	unneback	`output fifo_full;`
464			`input wclk, rclk, rst;`
465
466			`ifndef GENERATE_DIRECTION_AS_LATCH
467			`wire direction;`
468			`endif
469			`ifdef GENERATE_DIRECTION_AS_LATCH
470			`reg direction;`
471			`endif
472			`reg direction_set, direction_clr;`
473
474			`wire async_empty, async_full;`
475			`wire fifo_full2;`
476	14	unneback	`wire fifo_empty2;`
477	5	unneback
478			`// direction_set`
479			`always @ (wptr[N:N-1] or rptr[N:N-1])`
480			`case ({wptr[N:N-1],rptr[N:N-1]})`
481			`{Q1,Q2} : direction_set <= 1'b1;`
482			`{Q2,Q3} : direction_set <= 1'b1;`
483			`{Q3,Q4} : direction_set <= 1'b1;`
484			`{Q4,Q1} : direction_set <= 1'b1;`
485			`default : direction_set <= 1'b0;`
486			`endcase`
487
488			`// direction_clear`
489			`always @ (wptr[N:N-1] or rptr[N:N-1] or rst)`
490			`if (rst)`
491			`direction_clr <= 1'b1;`
492			`else`
493			`case ({wptr[N:N-1],rptr[N:N-1]})`
494			`{Q2,Q1} : direction_clr <= 1'b1;`
495			`{Q3,Q2} : direction_clr <= 1'b1;`
496			`{Q4,Q3} : direction_clr <= 1'b1;`
497			`{Q1,Q4} : direction_clr <= 1'b1;`
498			`default : direction_clr <= 1'b0;`
499			`endcase`
500

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