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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter mem_size = 256;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
//E2_ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
   reg [data_width-1:0] ram [mem_size-1:0];
//E2_endif
 
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
always_ff@(posedge clk)
begin
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
    end
    q <= ram[adr];
end
 
//E2_else
 
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
//E2_endif
 
endmodule
`endif
 
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
// Content addresable memory, CAM
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef REG_FILE
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
    always @ (negedge clk)
    if (we3_reg)
        ram1[a3_reg] <= wd3;
    always @ (posedge clk)
        a1_reg <= a1;
    assign rd1 = ram1[a1_reg];
 
    always @ (negedge clk)
    if (we3_reg)
        ram2[a3_reg] <= wd3;
    always @ (posedge clk)
        a2_reg <= a2;
    assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram1 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd1),
        .adr_b(a1),
        .clk_b(clk) );
 
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram2 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd2),
        .adr_b(a2),
        .clk_b(clk) );
`undef MODULE
 
`endif
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51			`input [(addr_width-1):0] adr;`
52			`output reg [(data_width-1):0] q;`
53			`input clk;`
54			`reg [data_width-1:0] rom [(1<<addr_width)-1:0];`
55			`parameter memory_file = "vl_rom.vmem";`
56			`initial`
57			`begin`
58			`$readmemh(memory_file, rom);`
59			`end`
60
61			`always @ (posedge clk)`
62			`q <= rom[adr];`
63	5	unneback
64	7	unneback	`endmodule`
65	40	unneback	`endif
66	7	unneback
67	40	unneback	`ifdef RAM
68			`define MODULE ram
69	5	unneback	`// Single port RAM`
70	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
71			`undef MODULE
72	5	unneback
73			`parameter data_width = 32;`
74			`parameter addr_width = 8;`
75			`input [(data_width-1):0] d;`
76			`input [(addr_width-1):0] adr;`
77			`input we;`
78	7	unneback	`output reg [(data_width-1):0] q;`
79	5	unneback	`input clk;`
80			`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`
81	7	unneback	`parameter init = 0;`
82			`parameter memory_file = "vl_ram.vmem";`
83			`generate if (init) begin : init_mem`
84			`initial`
85			`begin`
86			`$readmemh(memory_file, ram);`
87			`end`
88			`end`
89			`endgenerate`
90
91	5	unneback	`always @ (posedge clk)`
92			`begin`
93			`if (we)`
94			`ram[adr] <= d;`
95			`q <= ram[adr];`
96			`end`
97
98			`endmodule`
99	40	unneback	`endif
100	5	unneback
101	40	unneback	`ifdef RAM_BE
102			`define MODULE ram_be
103			module `BASE`MODULE ( d, adr, be, we, q, clk);
104			`undef MODULE
105
106	7	unneback	`parameter data_width = 32;`
107	72	unneback	`parameter addr_width = 6;`
108	68	unneback	`parameter mem_size = 256;`
109	7	unneback	`input [(data_width-1):0] d;`
110			`input [(addr_width-1):0] adr;`
111	73	unneback	`input [(data_width/8)-1:0] be;`
112	7	unneback	`input we;`
113			`output reg [(data_width-1):0] q;`
114			`input clk;`
115
116	65	unneback	`//E2_ifdef SYSTEMVERILOG`
117	68	unneback	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`
118	65	unneback	`//E2_else`
119	68	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
120	65	unneback	`//E2_endif`
121
122	60	unneback	`parameter memory_init = 0;`
123	7	unneback	`parameter memory_file = "vl_ram.vmem";`
124	60	unneback	`generate if (memory_init) begin : init_mem`
125	7	unneback	`initial`
126			`begin`
127			`$readmemh(memory_file, ram);`
128			`end`
129			`end`
130			`endgenerate`
131
132	60	unneback	`//E2_ifdef SYSTEMVERILOG`
133			`// use a multi-dimensional packed array`
134			`//to model individual bytes within the word`
135
136			`always_ff@(posedge clk)`
137			`begin`
138			`if(we) begin // note: we should have a for statement to support any bus width`
139	65	unneback	`if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];`
140			`if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];`
141			`if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];`
142			`if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];`
143	60	unneback	`end`
144	65	unneback	`q <= ram[adr];`
145	60	unneback	`end`
146
147			`//E2_else`
148
149	7	unneback	`genvar i;`
150			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram`
151			`always @ (posedge clk)`
152			`if (we & be[i])`
153			`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
154			`end`
155			`endgenerate`
156
157			`always @ (posedge clk)`
158			`q <= ram[adr];`
159
160	60	unneback	`//E2_endif`
161
162	7	unneback	`endmodule`
163	40	unneback	`endif
164	7	unneback
165	5	unneback	`ifdef ACTEL
166	48	unneback	`// ACTEL FPGA should not use logic to handle rw collision`
167	5	unneback	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
168			`else
169			`define SYN
170			`endif
171
172	40	unneback	`ifdef DPRAM_1R1W
173			`define MODULE dpram_1r1w
174			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
175			`undef MODULE
176	5	unneback	`parameter data_width = 32;`
177			`parameter addr_width = 8;`
178			`input [(data_width-1):0] d_a;`
179			`input [(addr_width-1):0] adr_a;`
180			`input [(addr_width-1):0] adr_b;`
181			`input we_a;`
182			`output [(data_width-1):0] q_b;`
183			`input clk_a, clk_b;`
184			`reg [(addr_width-1):0] adr_b_reg;`
185			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
186	7	unneback
187			`parameter init = 0;`
188			`parameter memory_file = "vl_ram.vmem";`
189			`generate if (init) begin : init_mem`
190			`initial`
191			`begin`
192			`$readmemh(memory_file, ram);`
193			`end`
194			`end`
195			`endgenerate`
196
197	5	unneback	`always @ (posedge clk_a)`
198			`if (we_a)`
199			`ram[adr_a] <= d_a;`
200			`always @ (posedge clk_b)`
201			`adr_b_reg <= adr_b;`
202			`assign q_b = ram[adr_b_reg];`
203	40	unneback
204	5	unneback	`endmodule`
205	40	unneback	`endif
206	5	unneback
207	40	unneback	`ifdef DPRAM_2R1W
208			`define MODULE dpram_2r1w
209			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
210			`undef MODULE
211
212	5	unneback	`parameter data_width = 32;`
213			`parameter addr_width = 8;`
214			`input [(data_width-1):0] d_a;`
215			`input [(addr_width-1):0] adr_a;`
216			`input [(addr_width-1):0] adr_b;`
217			`input we_a;`
218			`output [(data_width-1):0] q_b;`
219			`output reg [(data_width-1):0] q_a;`
220			`input clk_a, clk_b;`
221			`reg [(data_width-1):0] q_b;`
222			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
223	7	unneback
224			`parameter init = 0;`
225			`parameter memory_file = "vl_ram.vmem";`
226			`generate if (init) begin : init_mem`
227			`initial`
228			`begin`
229			`$readmemh(memory_file, ram);`
230			`end`
231			`end`
232			`endgenerate`
233
234	5	unneback	`always @ (posedge clk_a)`
235			`begin`
236			`q_a <= ram[adr_a];`
237			`if (we_a)`
238			`ram[adr_a] <= d_a;`
239			`end`
240			`always @ (posedge clk_b)`
241			`q_b <= ram[adr_b];`
242			`endmodule`
243	40	unneback	`endif
244	5	unneback
245	40	unneback	`ifdef DPRAM_2R2W
246			`define MODULE dpram_2r2w
247			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
248			`undef MODULE
249
250	5	unneback	`parameter data_width = 32;`
251			`parameter addr_width = 8;`
252			`input [(data_width-1):0] d_a;`
253			`input [(addr_width-1):0] adr_a;`
254			`input [(addr_width-1):0] adr_b;`
255			`input we_a;`
256			`output [(data_width-1):0] q_b;`
257			`input [(data_width-1):0] d_b;`
258			`output reg [(data_width-1):0] q_a;`
259			`input we_b;`
260			`input clk_a, clk_b;`
261			`reg [(data_width-1):0] q_b;`
262			reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
263	7	unneback
264			`parameter init = 0;`
265			`parameter memory_file = "vl_ram.vmem";`
266			`generate if (init) begin : init_mem`
267			`initial`
268			`begin`
269			`$readmemh(memory_file, ram);`
270			`end`
271			`end`
272			`endgenerate`
273
274	5	unneback	`always @ (posedge clk_a)`
275			`begin`
276			`q_a <= ram[adr_a];`
277			`if (we_a)`
278			`ram[adr_a] <= d_a;`
279			`end`
280			`always @ (posedge clk_b)`
281			`begin`
282			`q_b <= ram[adr_b];`
283			`if (we_b)`
284			`ram[adr_b] <= d_b;`
285			`end`
286			`endmodule`
287	40	unneback	`endif
288	5	unneback
289			`// Content addresable memory, CAM`
290
291	40	unneback	`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
292	5	unneback	`// FIFO`
293	40	unneback	`define MODULE fifo_1r1w_fill_level_sync
294			module `BASE`MODULE (
295			`undef MODULE
296	25	unneback	`d, wr, fifo_full,`
297			`q, rd, fifo_empty,`
298			`fill_level,`
299			`clk, rst`
300			`);`
301
302			`parameter data_width = 18;`
303			`parameter addr_width = 4;`
304	5	unneback
305	25	unneback	`// write side`
306			`input [data_width-1:0] d;`
307			`input wr;`
308			`output fifo_full;`
309			`// read side`
310			`output [data_width-1:0] q;`
311			`input rd;`
312			`output fifo_empty;`
313			`// common`
314			`output [addr_width:0] fill_level;`
315			`input rst, clk;`
316
317			`wire [addr_width:1] wadr, radr;`
318
319	40	unneback	`define MODULE cnt_bin_ce
320			`BASE`MODULE
321	25	unneback	`# ( .length(addr_width))`
322			`fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));`
323	40	unneback	`BASE`MODULE
324	25	unneback	`# (.length(addr_width))`
325			`fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));`
326	40	unneback	`undef MODULE
327	25	unneback
328	40	unneback	`define MODULE dpram_1r1w
329			`BASE`MODULE
330	25	unneback	`# (.data_width(data_width), .addr_width(addr_width))`
331			`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`
332	40	unneback	`undef MODULE
333	25	unneback
334	40	unneback	`define MODULE cnt_bin_ce_rew_q_zq_l1
335			`BASE`MODULE
336	27	unneback	`# (.length(addr_width+1), .level1_value(1<<addr_width))`
337	25	unneback	`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`
338	40	unneback	`undef MODULE
339	25	unneback	`endmodule`
340	40	unneback	`endif
341	25	unneback
342	40	unneback	`ifdef FIFO_2R2W_SYNC_SIMPLEX
343	27	unneback	`// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource`
344			`// RAM is supposed to be larger than the two FIFOs`
345			`// LFSR counters used adr pointers`
346	40	unneback	`define MODULE fifo_2r2w_sync_simplex
347			module `BASE`MODULE (
348			`undef MODULE
349	27	unneback	`// a side`
350			`a_d, a_wr, a_fifo_full,`
351			`a_q, a_rd, a_fifo_empty,`
352			`a_fill_level,`
353			`// b side`
354			`b_d, b_wr, b_fifo_full,`
355			`b_q, b_rd, b_fifo_empty,`
356			`b_fill_level,`
357			`// common`
358			`clk, rst`
359			`);`
360			`parameter data_width = 8;`
361			`parameter addr_width = 5;`
362			`parameter fifo_full_level = (1<<addr_width)-1;`
363
364			`// a side`
365			`input [data_width-1:0] a_d;`
366			`input a_wr;`
367			`output a_fifo_full;`
368			`output [data_width-1:0] a_q;`
369			`input a_rd;`
370			`output a_fifo_empty;`
371			`output [addr_width-1:0] a_fill_level;`
372
373			`// b side`
374			`input [data_width-1:0] b_d;`
375			`input b_wr;`
376			`output b_fifo_full;`
377			`output [data_width-1:0] b_q;`
378			`input b_rd;`
379			`output b_fifo_empty;`
380			`output [addr_width-1:0] b_fill_level;`
381
382			`input clk;`
383			`input rst;`
384
385			`// adr_gen`
386			`wire [addr_width:1] a_wadr, a_radr;`
387			`wire [addr_width:1] b_wadr, b_radr;`
388			`// dpram`
389			`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
390
391	40	unneback	`define MODULE cnt_lfsr_ce
392			`BASE`MODULE
393	27	unneback	`# ( .length(addr_width))`
394			`fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));`
395
396	40	unneback	`BASE`MODULE
397	27	unneback	`# (.length(addr_width))`
398			`fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));`
399
400	40	unneback	`BASE`MODULE
401	27	unneback	`# ( .length(addr_width))`
402			`fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));`
403
404	40	unneback	`BASE`MODULE
405	27	unneback	`# (.length(addr_width))`
406			`fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));`
407	40	unneback	`undef MODULE
408	27	unneback
409			`// mux read or write adr to DPRAM`
410			`assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};`
411			`assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};`
412
413	40	unneback	`define MODULE dpram_2r2w
414			`BASE`MODULE
415	27	unneback	`# (.data_width(data_width), .addr_width(addr_width+1))`
416			`dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),`
417			`.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));`
418	40	unneback	`undef MODULE
419
420			`define MODULE cnt_bin_ce_rew_zq_l1
421			`BASE`MODULE
422	28	unneback	`# (.length(addr_width), .level1_value(fifo_full_level))`
423	27	unneback	`a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));`
424
425	40	unneback	`BASE`MODULE
426	28	unneback	`# (.length(addr_width), .level1_value(fifo_full_level))`
427	27	unneback	`b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));`
428	40	unneback	`undef MODULE
429	27	unneback
430			`endmodule`
431	40	unneback	`endif
432	27	unneback
433	40	unneback	`ifdef FIFO_CMP_ASYNC
434			`define MODULE fifo_cmp_async
435			module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
436			`undef MODULE
437	5	unneback
438	11	unneback	`parameter addr_width = 4;`
439			`parameter N = addr_width-1;`
440	5	unneback
441			`parameter Q1 = 2'b00;`
442			`parameter Q2 = 2'b01;`
443			`parameter Q3 = 2'b11;`
444			`parameter Q4 = 2'b10;`
445
446			`parameter going_empty = 1'b0;`
447			`parameter going_full = 1'b1;`
448
449			`input [N:0] wptr, rptr;`
450	14	unneback	`output fifo_empty;`
451	5	unneback	`output fifo_full;`
452			`input wclk, rclk, rst;`
453
454			`ifndef GENERATE_DIRECTION_AS_LATCH
455			`wire direction;`
456			`endif
457			`ifdef GENERATE_DIRECTION_AS_LATCH
458			`reg direction;`
459			`endif
460			`reg direction_set, direction_clr;`
461
462			`wire async_empty, async_full;`
463			`wire fifo_full2;`
464	14	unneback	`wire fifo_empty2;`
465	5	unneback
466			`// direction_set`
467			`always @ (wptr[N:N-1] or rptr[N:N-1])`
468			`case ({wptr[N:N-1],rptr[N:N-1]})`
469			`{Q1,Q2} : direction_set <= 1'b1;`
470			`{Q2,Q3} : direction_set <= 1'b1;`
471			`{Q3,Q4} : direction_set <= 1'b1;`
472			`{Q4,Q1} : direction_set <= 1'b1;`
473			`default : direction_set <= 1'b0;`
474			`endcase`
475
476			`// direction_clear`
477			`always @ (wptr[N:N-1] or rptr[N:N-1] or rst)`
478			`if (rst)`
479			`direction_clr <= 1'b1;`
480			`else`
481			`case ({wptr[N:N-1],rptr[N:N-1]})`
482			`{Q2,Q1} : direction_clr <= 1'b1;`
483			`{Q3,Q2} : direction_clr <= 1'b1;`
484			`{Q4,Q3} : direction_clr <= 1'b1;`
485			`{Q1,Q4} : direction_clr <= 1'b1;`
486			`default : direction_clr <= 1'b0;`
487			`endcase`
488
489	40	unneback	`define MODULE dff_sr
490	5	unneback	`ifndef GENERATE_DIRECTION_AS_LATCH
491	40	unneback	`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
492	5	unneback	`endif
493
494			`ifdef GENERATE_DIRECTION_AS_LATCH
495			`always @ (posedge direction_set or posedge direction_clr)`
496			`if (direction_clr)`
497			`direction <= going_empty;`
498			`else`
499			`direction <= going_full;`
500			`endif

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