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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [mem_size-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [mem_szie-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
 
//E2_ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
    reg [data_width-1:0] ram [mem_size-1:0];
    wire [data_width/8-1:0] cke;
//E2_endif
 
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
always_ff@(posedge clk)
begin
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
        q <= ram[adr];
end
 
//E2_else
 
assign cke = {data_width/8{we}} & be;
   genvar i;
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (cke[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
//E2_endif
 
//E2_ifdef verilator
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
   endfunction // get_mem
 
   // Function to write RAM (for use by Verilator).
   function set_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      input [data_width-1:0]             data;
      ram[addr] = data;
   endfunction // set_mem
//E2_endif
 
endmodule
`endif
 
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter b_data_width = a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_data_width/8-1):0]    be_a;
   input                           we_a;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width-1):0]       d_b;
   input [(b_addr_width-1):0]       adr_b;
   input [(b_data_width/8-1):0]    be_b;
   input                           we_b;
   output reg [(b_data_width-1):0]          q_b;
   input                           clk_a, clk_b;
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
   logic [3:0][7:0] ram [0:mem_size-1];
 
    always_ff@(posedge clk_a)
    begin
        if(we_a) begin
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
        end
    end
 
    always@(posedge clk_a)
        q_a = ram[adr_a];
 
    always_ff@(posedge clk_b)
    begin
        if(we_b) begin
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
        end
    end
 
    always@(posedge clk_b)
        q_b = ram[adr_b];
 
end
endgenerate
 
//E2_else
    // This modules requires SystemVerilog
//E2_endif
endmodule
`endif
 
`ifdef CAM
// Content addresable memory, CAM
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef REG_FILE
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
    always @ (negedge clk)
    if (we3_reg)
        ram1[a3_reg] <= wd3;
    always @ (posedge clk)
        a1_reg <= a1;
    assign rd1 = ram1[a1_reg];
 
    always @ (negedge clk)
    if (we3_reg)
        ram2[a3_reg] <= wd3;
    always @ (posedge clk)
        a2_reg <= a2;
    assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram1 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd1),
        .adr_b(a1),
        .clk_b(clk) );
 
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram2 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd2),
        .adr_b(a2),
        .clk_b(clk) );
`undef MODULE
 
`endif
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51	75	unneback	`parameter mem_size = 1<<addr_width;`
52	7	unneback	`input [(addr_width-1):0] adr;`
53			`output reg [(data_width-1):0] q;`
54			`input clk;`
55	75	unneback	`reg [data_width-1:0] rom [mem_size-1:0];`
56	7	unneback	`parameter memory_file = "vl_rom.vmem";`
57			`initial`
58			`begin`
59			`$readmemh(memory_file, rom);`
60			`end`
61
62			`always @ (posedge clk)`
63			`q <= rom[adr];`
64	5	unneback
65	7	unneback	`endmodule`
66	40	unneback	`endif
67	7	unneback
68	40	unneback	`ifdef RAM
69			`define MODULE ram
70	5	unneback	`// Single port RAM`
71	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
72			`undef MODULE
73	5	unneback
74			`parameter data_width = 32;`
75			`parameter addr_width = 8;`
76	75	unneback	`parameter mem_size = 1<<addr_width;`
77	5	unneback	`input [(data_width-1):0] d;`
78			`input [(addr_width-1):0] adr;`
79			`input we;`
80	7	unneback	`output reg [(data_width-1):0] q;`
81	5	unneback	`input clk;`
82	75	unneback	`reg [data_width-1:0] ram [mem_szie-1:0];`
83	7	unneback	`parameter init = 0;`
84			`parameter memory_file = "vl_ram.vmem";`
85			`generate if (init) begin : init_mem`
86			`initial`
87			`begin`
88			`$readmemh(memory_file, ram);`
89			`end`
90			`end`
91			`endgenerate`
92
93	5	unneback	`always @ (posedge clk)`
94			`begin`
95			`if (we)`
96			`ram[adr] <= d;`
97			`q <= ram[adr];`
98			`end`
99
100			`endmodule`
101	40	unneback	`endif
102	5	unneback
103	40	unneback	`ifdef RAM_BE
104			`define MODULE ram_be
105	91	unneback	module `BASE`MODULE ( d, adr, be, we, q, clk);
106	40	unneback	`undef MODULE
107
108	7	unneback	`parameter data_width = 32;`
109	72	unneback	`parameter addr_width = 6;`
110	75	unneback	`parameter mem_size = 1<<addr_width;`
111	7	unneback	`input [(data_width-1):0] d;`
112			`input [(addr_width-1):0] adr;`
113	73	unneback	`input [(data_width/8)-1:0] be;`
114	7	unneback	`input we;`
115			`output reg [(data_width-1):0] q;`
116			`input clk;`
117
118	84	unneback
119	65	unneback	`//E2_ifdef SYSTEMVERILOG`
120	68	unneback	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`
121	65	unneback	`//E2_else`
122	84	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
123			`wire [data_width/8-1:0] cke;`
124	65	unneback	`//E2_endif`
125
126	60	unneback	`parameter memory_init = 0;`
127	7	unneback	`parameter memory_file = "vl_ram.vmem";`
128	60	unneback	`generate if (memory_init) begin : init_mem`
129	7	unneback	`initial`
130			`begin`
131			`$readmemh(memory_file, ram);`
132			`end`
133			`end`
134			`endgenerate`
135
136	60	unneback	`//E2_ifdef SYSTEMVERILOG`
137			`// use a multi-dimensional packed array`
138			`//to model individual bytes within the word`
139
140			`always_ff@(posedge clk)`
141			`begin`
142			`if(we) begin // note: we should have a for statement to support any bus width`
143	86	unneback	`if(be[3]) ram[adr][3] <= d[31:24];`
144			`if(be[2]) ram[adr][2] <= d[23:16];`
145			`if(be[1]) ram[adr][1] <= d[15:8];`
146			`if(be[0]) ram[adr][0] <= d[7:0];`
147	60	unneback	`end`
148	90	unneback	`q <= ram[adr];`
149	60	unneback	`end`
150
151			`//E2_else`
152
153	84	unneback	`assign cke = {data_width/8{we}} & be;`
154	7	unneback	`genvar i;`
155	84	unneback	`generate for (i=0;i<data_width/8;i=i+1) begin : be_ram`
156	7	unneback	`always @ (posedge clk)`
157	84	unneback	`if (cke[i])`
158	7	unneback	`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
159			`end`
160			`endgenerate`
161
162			`always @ (posedge clk)`
163			`q <= ram[adr];`
164
165	60	unneback	`//E2_endif`
166
167	93	unneback	`//E2_ifdef verilator`
168	84	unneback	`// Function to access RAM (for use by Verilator).`
169			`function [31:0] get_mem;`
170			`// verilator public`
171	90	unneback	`input [addr_width-1:0] addr;`
172	84	unneback	`get_mem = ram[addr];`
173			`endfunction // get_mem`
174
175			`// Function to write RAM (for use by Verilator).`
176			`function set_mem;`
177			`// verilator public`
178	90	unneback	`input [addr_width-1:0] addr;`
179			`input [data_width-1:0] data;`
180	84	unneback	`ram[addr] = data;`
181			`endfunction // set_mem`
182	93	unneback	`//E2_endif`
183	84	unneback
184	7	unneback	`endmodule`
185	40	unneback	`endif
186	7	unneback
187	5	unneback	`ifdef ACTEL
188	48	unneback	`// ACTEL FPGA should not use logic to handle rw collision`
189	5	unneback	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
190			`else
191			`define SYN
192			`endif
193
194	40	unneback	`ifdef DPRAM_1R1W
195			`define MODULE dpram_1r1w
196			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
197			`undef MODULE
198	5	unneback	`parameter data_width = 32;`
199			`parameter addr_width = 8;`
200	75	unneback	`parameter mem_size = 1<<addr_width;`
201	5	unneback	`input [(data_width-1):0] d_a;`
202			`input [(addr_width-1):0] adr_a;`
203			`input [(addr_width-1):0] adr_b;`
204			`input we_a;`
205			`output [(data_width-1):0] q_b;`
206			`input clk_a, clk_b;`
207			`reg [(addr_width-1):0] adr_b_reg;`
208	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
209	7	unneback
210			`parameter init = 0;`
211			`parameter memory_file = "vl_ram.vmem";`
212			`generate if (init) begin : init_mem`
213			`initial`
214			`begin`
215			`$readmemh(memory_file, ram);`
216			`end`
217			`end`
218			`endgenerate`
219
220	5	unneback	`always @ (posedge clk_a)`
221			`if (we_a)`
222			`ram[adr_a] <= d_a;`
223			`always @ (posedge clk_b)`
224			`adr_b_reg <= adr_b;`
225			`assign q_b = ram[adr_b_reg];`
226	40	unneback
227	5	unneback	`endmodule`
228	40	unneback	`endif
229	5	unneback
230	40	unneback	`ifdef DPRAM_2R1W
231			`define MODULE dpram_2r1w
232			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
233			`undef MODULE
234
235	5	unneback	`parameter data_width = 32;`
236			`parameter addr_width = 8;`
237	75	unneback	`parameter mem_size = 1<<addr_width;`
238	5	unneback	`input [(data_width-1):0] d_a;`
239			`input [(addr_width-1):0] adr_a;`
240			`input [(addr_width-1):0] adr_b;`
241			`input we_a;`
242			`output [(data_width-1):0] q_b;`
243			`output reg [(data_width-1):0] q_a;`
244			`input clk_a, clk_b;`
245			`reg [(data_width-1):0] q_b;`
246	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
247	7	unneback
248			`parameter init = 0;`
249			`parameter memory_file = "vl_ram.vmem";`
250			`generate if (init) begin : init_mem`
251			`initial`
252			`begin`
253			`$readmemh(memory_file, ram);`
254			`end`
255			`end`
256			`endgenerate`
257
258	5	unneback	`always @ (posedge clk_a)`
259			`begin`
260			`q_a <= ram[adr_a];`
261			`if (we_a)`
262			`ram[adr_a] <= d_a;`
263			`end`
264			`always @ (posedge clk_b)`
265			`q_b <= ram[adr_b];`
266			`endmodule`
267	40	unneback	`endif
268	5	unneback
269	40	unneback	`ifdef DPRAM_2R2W
270			`define MODULE dpram_2r2w
271			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
272			`undef MODULE
273
274	5	unneback	`parameter data_width = 32;`
275			`parameter addr_width = 8;`
276	75	unneback	`parameter mem_size = 1<<addr_width;`
277	5	unneback	`input [(data_width-1):0] d_a;`
278			`input [(addr_width-1):0] adr_a;`
279			`input [(addr_width-1):0] adr_b;`
280			`input we_a;`
281			`output [(data_width-1):0] q_b;`
282			`input [(data_width-1):0] d_b;`
283			`output reg [(data_width-1):0] q_a;`
284			`input we_b;`
285			`input clk_a, clk_b;`
286			`reg [(data_width-1):0] q_b;`
287	75	unneback	reg [data_width-1:0] ram [mem_size-1:0] `SYN;
288	7	unneback
289			`parameter init = 0;`
290			`parameter memory_file = "vl_ram.vmem";`
291			`generate if (init) begin : init_mem`
292			`initial`
293			`begin`
294			`$readmemh(memory_file, ram);`
295			`end`
296			`end`
297			`endgenerate`
298
299	5	unneback	`always @ (posedge clk_a)`
300			`begin`
301			`q_a <= ram[adr_a];`
302			`if (we_a)`
303			`ram[adr_a] <= d_a;`
304			`end`
305			`always @ (posedge clk_b)`
306			`begin`
307			`q_b <= ram[adr_b];`
308			`if (we_b)`
309			`ram[adr_b] <= d_b;`
310			`end`
311			`endmodule`
312	40	unneback	`endif
313	5	unneback
314	83	unneback
315	75	unneback	`ifdef DPRAM_BE_2R2W
316			`define MODULE dpram_be_2r2w
317	92	unneback	module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
318	75	unneback	`undef MODULE
319
320			`parameter a_data_width = 32;`
321			`parameter a_addr_width = 8;`
322	92	unneback	`parameter b_data_width = a_data_width;`
323	91	unneback	`localparam b_addr_width = a_data_width * a_addr_width / b_data_width;`
324			`parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);`
325
326	75	unneback	`input [(a_data_width-1):0] d_a;`
327	91	unneback	`input [(a_addr_width-1):0] adr_a;`
328			`input [(a_data_width/8-1):0] be_a;`
329			`input we_a;`
330	75	unneback	`output reg [(a_data_width-1):0] q_a;`
331	91	unneback	`input [(b_data_width-1):0] d_b;`
332			`input [(b_addr_width-1):0] adr_b;`
333	92	unneback	`input [(b_data_width/8-1):0] be_b;`
334			`input we_b;`
335			`output reg [(b_data_width-1):0] q_b;`
336	91	unneback	`input clk_a, clk_b;`
337	75	unneback
338	91	unneback	`//E2_ifdef SYSTEMVERILOG`
339			`// use a multi-dimensional packed array`
340			`//to model individual bytes within the word`
341
342	75	unneback	`generate`
343	91	unneback	`if (a_data_width==32 & b_data_width==32) begin : dpram_3232`
344	75	unneback
345	91	unneback	`logic [3:0][7:0] ram [0:mem_size-1];`
346
347			`always_ff@(posedge clk_a)`
348			`begin`
349			`if(we_a) begin`
350			`if(be_a[3]) ram[adr_a][3] <= d_a[31:24];`
351			`if(be_a[2]) ram[adr_a][2] <= d_a[23:16];`
352			`if(be_a[1]) ram[adr_a][1] <= d_a[15:8];`
353			`if(be_a[0]) ram[adr_a][0] <= d_a[7:0];`
354			`end`
355			`end`
356
357	92	unneback	`always@(posedge clk_a)`
358			`q_a = ram[adr_a];`
359	91	unneback
360			`always_ff@(posedge clk_b)`
361	92	unneback	`begin`
362			`if(we_b) begin`
363			`if(be_b[3]) ram[adr_b][3] <= d_b[31:24];`
364			`if(be_b[2]) ram[adr_b][2] <= d_b[23:16];`
365			`if(be_b[1]) ram[adr_b][1] <= d_b[15:8];`
366			`if(be_b[0]) ram[adr_b][0] <= d_b[7:0];`
367			`end`
368			`end`
369	91	unneback
370	92	unneback	`always@(posedge clk_b)`
371			`q_b = ram[adr_b];`
372	91	unneback
373	75	unneback	`end`
374			`endgenerate`
375
376	91	unneback	`//E2_else`
377	92	unneback	`// This modules requires SystemVerilog`
378	91	unneback	`//E2_endif`
379	75	unneback	`endmodule`
380			`endif
381
382	91	unneback	`ifdef CAM
383	5	unneback	`// Content addresable memory, CAM`
384	91	unneback	`endif
385	5	unneback
386	40	unneback	`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
387	5	unneback	`// FIFO`
388	40	unneback	`define MODULE fifo_1r1w_fill_level_sync
389			module `BASE`MODULE (
390			`undef MODULE
391	25	unneback	`d, wr, fifo_full,`
392			`q, rd, fifo_empty,`
393			`fill_level,`
394			`clk, rst`
395			`);`
396
397			`parameter data_width = 18;`
398			`parameter addr_width = 4;`
399	5	unneback
400	25	unneback	`// write side`
401			`input [data_width-1:0] d;`
402			`input wr;`
403			`output fifo_full;`
404			`// read side`
405			`output [data_width-1:0] q;`
406			`input rd;`
407			`output fifo_empty;`
408			`// common`
409			`output [addr_width:0] fill_level;`
410			`input rst, clk;`
411
412			`wire [addr_width:1] wadr, radr;`
413
414	40	unneback	`define MODULE cnt_bin_ce
415			`BASE`MODULE
416	25	unneback	`# ( .length(addr_width))`
417			`fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));`
418	40	unneback	`BASE`MODULE
419	25	unneback	`# (.length(addr_width))`
420			`fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));`
421	40	unneback	`undef MODULE
422	25	unneback
423	40	unneback	`define MODULE dpram_1r1w
424			`BASE`MODULE
425	25	unneback	`# (.data_width(data_width), .addr_width(addr_width))`
426			`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`
427	40	unneback	`undef MODULE
428	25	unneback
429	40	unneback	`define MODULE cnt_bin_ce_rew_q_zq_l1
430			`BASE`MODULE
431	27	unneback	`# (.length(addr_width+1), .level1_value(1<<addr_width))`
432	25	unneback	`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`
433	40	unneback	`undef MODULE
434	25	unneback	`endmodule`
435	40	unneback	`endif
436	25	unneback
437	40	unneback	`ifdef FIFO_2R2W_SYNC_SIMPLEX
438	27	unneback	`// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource`
439			`// RAM is supposed to be larger than the two FIFOs`
440			`// LFSR counters used adr pointers`
441	40	unneback	`define MODULE fifo_2r2w_sync_simplex
442			module `BASE`MODULE (
443			`undef MODULE
444	27	unneback	`// a side`
445			`a_d, a_wr, a_fifo_full,`
446			`a_q, a_rd, a_fifo_empty,`
447			`a_fill_level,`
448			`// b side`
449			`b_d, b_wr, b_fifo_full,`
450			`b_q, b_rd, b_fifo_empty,`
451			`b_fill_level,`
452			`// common`
453			`clk, rst`
454			`);`
455			`parameter data_width = 8;`
456			`parameter addr_width = 5;`
457			`parameter fifo_full_level = (1<<addr_width)-1;`
458
459			`// a side`
460			`input [data_width-1:0] a_d;`
461			`input a_wr;`
462			`output a_fifo_full;`
463			`output [data_width-1:0] a_q;`
464			`input a_rd;`
465			`output a_fifo_empty;`
466			`output [addr_width-1:0] a_fill_level;`
467
468			`// b side`
469			`input [data_width-1:0] b_d;`
470			`input b_wr;`
471			`output b_fifo_full;`
472			`output [data_width-1:0] b_q;`
473			`input b_rd;`
474			`output b_fifo_empty;`
475			`output [addr_width-1:0] b_fill_level;`
476
477			`input clk;`
478			`input rst;`
479
480			`// adr_gen`
481			`wire [addr_width:1] a_wadr, a_radr;`
482			`wire [addr_width:1] b_wadr, b_radr;`
483			`// dpram`
484			`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
485
486	40	unneback	`define MODULE cnt_lfsr_ce
487			`BASE`MODULE
488	27	unneback	`# ( .length(addr_width))`
489			`fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));`
490
491	40	unneback	`BASE`MODULE
492	27	unneback	`# (.length(addr_width))`
493			`fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));`
494
495	40	unneback	`BASE`MODULE
496	27	unneback	`# ( .length(addr_width))`
497			`fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));`
498
499	40	unneback	`BASE`MODULE
500	27	unneback	`# (.length(addr_width))`

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