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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, registers                                ////
////                                                              ////
////  Description                                                 ////
////  Different type of registers                                 ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef DFF
`define MODULE dff
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
                q <= reset_value;
        else
                q <= d;
 
endmodule
`endif
 
`ifdef DFF_ARRAY
`define MODULE dff_array
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter depth = 2;
        parameter reset_value = 1'b0;
 
        input [width-1:0] d;
        input clk, rst;
        output [width-1:0] q;
        reg  [0:depth-1] q_tmp [width-1:0];
        integer i;
        always @ (posedge clk or posedge rst)
        if (rst) begin
            for (i=0;i<depth;i=i+1)
                q_tmp[i] <= {width{reset_value}};
        end else begin
            q_tmp[0] <= d;
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
        end
 
    assign q = q_tmp[depth-1];
 
endmodule
`endif
 
`ifdef DFF_CE
`define MODULE dff_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
                q <= reset_value;
        else
                if (ce)
                        q <= d;
 
endmodule
`endif
 
`ifdef DFF_CE_CLEAR
`define MODULE dff_ce_clear
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (ce)
                if (clear)
                    q <= {width{1'b0}};
                else
                    q <= d;
 
endmodule
`endif
 
`ifdef DF_CE_SET
`define MODULE dff_ce_set
module `BASE`MODULE ( d, ce, set, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (ce)
                if (set)
                    q <= {width{1'b1}};
                else
                    q <= d;
 
endmodule
`endif
 
`ifdef SPR
`define MODULE spr
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
 
        //parameter width = 1;
        parameter reset_value = 1'b0;
 
        input sp, r;
        output reg q;
        input clk, rst;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (sp)
                q <= 1'b1;
            else if (r)
                q <= 1'b0;
 
endmodule
`endif
 
`ifdef SRP
`define MODULE srp
module `BASE`MODULE ( s, rp, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input s, rp;
        output reg q;
        input clk, rst;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (rp)
                q <= 1'b0;
            else if (s)
                q <= 1'b1;
 
endmodule
`endif
 
`ifdef ALTERA
 
`ifdef DFF_SR
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff 
 
// ============================================================
// File Name: dff_sr.v
// Megafunction Name(s):
//                      lpm_ff
//
// Simulation Library Files(s):
//                      lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define MODULE dff_sr
module `BASE`MODULE (
`undef MODULE
 
        aclr,
        aset,
        clock,
        data,
        q);
 
        input     aclr;
        input     aset;
        input     clock;
        input     data;
        output    q;
 
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire  q = sub_wire1;
        wire  sub_wire2 = data;
        wire  sub_wire3 = sub_wire2;
 
        lpm_ff  lpm_ff_component (
                                .aclr (aclr),
                                .clock (clock),
                                .data (sub_wire3),
                                .aset (aset),
                                .q (sub_wire0)
                                // synopsys translate_off
                                ,
                                .aload (),
                                .enable (),
                                .sclr (),
                                .sload (),
                                .sset ()
                                // synopsys translate_on
                                );
        defparam
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_width = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
`endif
 
`else
 
`ifdef DFF_SR
`define MODULE dff_sr
module `BASE`MODULE ( aclr, aset, clock, data, q);
`undef MODULE
 
    input         aclr;
    input         aset;
    input         clock;
    input         data;
    output reg    q;
 
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
       q <= 1'b0;
     else if (aset)
       q <= 1'b1;
     else
       q <= data;
 
endmodule
`endif
 
`endif
 
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
 
`ifdef LATCH
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
input d, le;
output q;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
`endif
 
`else
 
`ifdef LATCH
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
input d, le;
input clk;
always @ (le or d)
if (le)
    d <= q;
endmodule
`endif
 
`endif
 
`ifdef SHREG
`define MODULE shreg
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
 
parameter depth = 10;
input d;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef SHREG_CE
`define MODULE shreg_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
parameter depth = 10;
input d, ce;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef DELAY
`define MODULE delay
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
parameter depth = 10;
input d;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef DELAY_EMPTYFLAG
`define MODULE delay_emptyflag
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
`undef MODULE
parameter depth = 10;
input d;
output q, emptyflag;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign emptyflag = !(|dffs);
endmodule
`endif
 
`ifdef ASYNC_REG_REQ_ACK
`define MODULE async_reg_req_ack
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
`undef MODULE
parameter data_width = 8;
input [data_width-1:0] d;
output [data_width-1:0] q;
input req_i;
output req_o;
input ack_i;
output ack_o;
input clk_a, rst_a, clk_b, rst_b;
 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
wire rst;
 
always @ (posedge clk_a or rst_a)
if (rst_a)
    q <= {data_width{1'b0}};
else
    if (req_i)
        q <= d;
 
assign rst = ack_i | rst_a;
always @ (posedge clk_a or posedge rst)
if (rst)
    req[2] <= 1'b0;
else
    req[2] <= req_i & !ack_o;
 
always @ (posedge clk_a or posedge rst_a)
if (rst_a)
    req[3] <= 1'b0;
else
    req[3] <= req[2];
 
always @ (posedge clk_b or posedge rst_b)
if (rst_b)
    req[1:0] <= 2'b00;
else
    if (ack_i)
        req[1:0] <= 2'b00;
    else
        req[1:0] <= req[2:1];
assign req_o = req[0];
 
always @ (posedge clk_a or posedge rst_a)
if (rst_a)
    ack_o <= 1'b0;
else
    ack_o <= req[3] & req[2];
 
endmodule
`endif

Line No.	Rev	Author	Line
1	3	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, registers ////`
4			`//// ////`
5			`//// Description ////`
6			`//// Different type of registers ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more different registers ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef DFF
44			`define MODULE dff
45			module `BASE`MODULE ( d, q, clk, rst);
46			`undef MODULE
47	3	unneback	`parameter width = 1;`
48			`parameter reset_value = 0;`
49
50			`input [width-1:0] d;`
51			`input clk, rst;`
52			`output reg [width-1:0] q;`
53
54			`always @ (posedge clk or posedge rst)`
55			`if (rst)`
56			`q <= reset_value;`
57			`else`
58			`q <= d;`
59
60			`endmodule`
61	40	unneback	`endif
62	3	unneback
63	40	unneback	`ifdef DFF_ARRAY
64			`define MODULE dff_array
65			module `BASE`MODULE ( d, q, clk, rst);
66			`undef MODULE
67	5	unneback
68			`parameter width = 1;`
69			`parameter depth = 2;`
70			`parameter reset_value = 1'b0;`
71
72			`input [width-1:0] d;`
73			`input clk, rst;`
74			`output [width-1:0] q;`
75			`reg [0:depth-1] q_tmp [width-1:0];`
76			`integer i;`
77			`always @ (posedge clk or posedge rst)`
78			`if (rst) begin`
79			`for (i=0;i<depth;i=i+1)`
80			`q_tmp[i] <= {width{reset_value}};`
81			`end else begin`
82			`q_tmp[0] <= d;`
83			`for (i=1;i<depth;i=i+1)`
84			`q_tmp[i] <= q_tmp[i-1];`
85			`end`
86
87			`assign q = q_tmp[depth-1];`
88
89			`endmodule`
90	40	unneback	`endif
91	5	unneback
92	40	unneback	`ifdef DFF_CE
93			`define MODULE dff_ce
94			module `BASE`MODULE ( d, ce, q, clk, rst);
95			`undef MODULE
96	3	unneback
97			`parameter width = 1;`
98			`parameter reset_value = 0;`
99
100			`input [width-1:0] d;`
101			`input ce, clk, rst;`
102			`output reg [width-1:0] q;`
103
104			`always @ (posedge clk or posedge rst)`
105			`if (rst)`
106			`q <= reset_value;`
107			`else`
108			`if (ce)`
109			`q <= d;`
110
111			`endmodule`
112	40	unneback	`endif
113	3	unneback
114	40	unneback	`ifdef DFF_CE_CLEAR
115			`define MODULE dff_ce_clear
116			module `BASE`MODULE ( d, ce, clear, q, clk, rst);
117			`undef MODULE
118	8	unneback
119			`parameter width = 1;`
120			`parameter reset_value = 0;`
121
122			`input [width-1:0] d;`
123	10	unneback	`input ce, clear, clk, rst;`
124	8	unneback	`output reg [width-1:0] q;`
125
126			`always @ (posedge clk or posedge rst)`
127			`if (rst)`
128			`q <= reset_value;`
129			`else`
130			`if (ce)`
131			`if (clear)`
132			`q <= {width{1'b0}};`
133			`else`
134			`q <= d;`
135
136			`endmodule`
137	40	unneback	`endif
138	8	unneback
139	40	unneback	`ifdef DF_CE_SET
140			`define MODULE dff_ce_set
141			module `BASE`MODULE ( d, ce, set, q, clk, rst);
142			`undef MODULE
143	24	unneback
144			`parameter width = 1;`
145			`parameter reset_value = 0;`
146
147			`input [width-1:0] d;`
148			`input ce, set, clk, rst;`
149			`output reg [width-1:0] q;`
150
151			`always @ (posedge clk or posedge rst)`
152			`if (rst)`
153			`q <= reset_value;`
154			`else`
155			`if (ce)`
156			`if (set)`
157			`q <= {width{1'b1}};`
158			`else`
159			`q <= d;`
160
161			`endmodule`
162	40	unneback	`endif
163	24	unneback
164	40	unneback	`ifdef SPR
165			`define MODULE spr
166			module `BASE`MODULE ( sp, r, q, clk, rst);
167			`undef MODULE
168
169	64	unneback	`//parameter width = 1;`
170			`parameter reset_value = 1'b0;`
171	29	unneback
172			`input sp, r;`
173			`output reg q;`
174			`input clk, rst;`
175
176			`always @ (posedge clk or posedge rst)`
177			`if (rst)`
178			`q <= reset_value;`
179			`else`
180			`if (sp)`
181			`q <= 1'b1;`
182			`else if (r)`
183			`q <= 1'b0;`
184
185			`endmodule`
186	40	unneback	`endif
187	29	unneback
188	40	unneback	`ifdef SRP
189			`define MODULE srp
190			module `BASE`MODULE ( s, rp, q, clk, rst);
191			`undef MODULE
192
193	29	unneback	`parameter width = 1;`
194			`parameter reset_value = 0;`
195
196			`input s, rp;`
197			`output reg q;`
198			`input clk, rst;`
199
200			`always @ (posedge clk or posedge rst)`
201			`if (rst)`
202			`q <= reset_value;`
203			`else`
204			`if (rp)`
205			`q <= 1'b0;`
206			`else if (s)`
207			`q <= 1'b1;`
208
209			`endmodule`
210	40	unneback	`endif
211	29	unneback
212	40	unneback	`ifdef ALTERA
213	29	unneback
214	40	unneback	`ifdef DFF_SR
215	3	unneback	`// megafunction wizard: %LPM_FF%`
216			`// GENERATION: STANDARD`
217			`// VERSION: WM1.0`
218			`// MODULE: lpm_ff`
219
220			`// ============================================================`
221			`// File Name: dff_sr.v`
222			`// Megafunction Name(s):`
223			`// lpm_ff`
224			`//`
225			`// Simulation Library Files(s):`
226			`// lpm`
227			`// ============================================================`
228			`// ************************************************************`
229			`// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!`
230			`//`
231			`// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version`
232			`// ************************************************************`
233
234
235			`//Copyright (C) 1991-2010 Altera Corporation`
236			`//Your use of Altera Corporation's design tools, logic functions`
237			`//and other software and tools, and its AMPP partner logic`
238			`//functions, and any output files from any of the foregoing`
239			`//(including device programming or simulation files), and any`
240			`//associated documentation or information are expressly subject`
241			`//to the terms and conditions of the Altera Program License`
242			`//Subscription Agreement, Altera MegaCore Function License`
243			`//Agreement, or other applicable license agreement, including,`
244			`//without limitation, that your use is for the sole purpose of`
245			`//programming logic devices manufactured by Altera and sold by`
246			`//Altera or its authorized distributors. Please refer to the`
247			`//applicable agreement for further details.`
248
249
250			`// synopsys translate_off`
251			`timescale 1 ps / 1 ps
252			`// synopsys translate_on`
253	40	unneback	`define MODULE dff_sr
254			module `BASE`MODULE (
255			`undef MODULE
256
257	3	unneback	`aclr,`
258			`aset,`
259			`clock,`
260			`data,`
261			`q);`
262
263			`input aclr;`
264			`input aset;`
265			`input clock;`
266			`input data;`
267			`output q;`
268
269			`wire [0:0] sub_wire0;`
270			`wire [0:0] sub_wire1 = sub_wire0[0:0];`
271			`wire q = sub_wire1;`
272			`wire sub_wire2 = data;`
273			`wire sub_wire3 = sub_wire2;`
274
275			`lpm_ff lpm_ff_component (`
276			`.aclr (aclr),`
277			`.clock (clock),`
278			`.data (sub_wire3),`
279			`.aset (aset),`
280			`.q (sub_wire0)`
281			`// synopsys translate_off`
282			`,`
283			`.aload (),`
284			`.enable (),`
285			`.sclr (),`
286			`.sload (),`
287			`.sset ()`
288			`// synopsys translate_on`
289			`);`
290			`defparam`
291			`lpm_ff_component.lpm_fftype = "DFF",`
292			`lpm_ff_component.lpm_type = "LPM_FF",`
293			`lpm_ff_component.lpm_width = 1;`
294
295
296			`endmodule`
297
298			`// ============================================================`
299			`// CNX file retrieval info`
300			`// ============================================================`
301			`// Retrieval info: PRIVATE: ACLR NUMERIC "1"`
302			`// Retrieval info: PRIVATE: ALOAD NUMERIC "0"`
303			`// Retrieval info: PRIVATE: ASET NUMERIC "1"`
304			`// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"`
305			`// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"`
306			`// Retrieval info: PRIVATE: DFF NUMERIC "1"`
307			`// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"`
308			`// Retrieval info: PRIVATE: SCLR NUMERIC "0"`
309			`// Retrieval info: PRIVATE: SLOAD NUMERIC "0"`
310			`// Retrieval info: PRIVATE: SSET NUMERIC "0"`
311			`// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"`
312			`// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"`
313			`// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"`
314			`// Retrieval info: PRIVATE: nBit NUMERIC "1"`
315			`// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"`
316			`// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"`
317			`// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"`
318			`// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr`
319			`// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset`
320			`// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock`
321			`// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data`
322			`// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q`
323			`// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0`
324			`// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0`
325			`// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0`
326			`// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0`
327			`// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0`
328			`// Retrieval info: LIBRARY: lpm lpm.lpm_components.all`
329			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE`
330			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE`
331			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE`
332			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE`
333			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE`
334			`// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE`
335			`// Retrieval info: LIB_FILE: lpm`
336	40	unneback	`endif
337	3	unneback
338			`else
339
340	40	unneback	`ifdef DFF_SR
341			`define MODULE dff_sr
342			module `BASE`MODULE ( aclr, aset, clock, data, q);
343			`undef MODULE
344	3	unneback
345			`input aclr;`
346			`input aset;`
347			`input clock;`
348			`input data;`
349			`output reg q;`
350
351			`always @ (posedge clock or posedge aclr or posedge aset)`
352			`if (aclr)`
353			`q <= 1'b0;`
354			`else if (aset)`
355			`q <= 1'b1;`
356			`else`
357			`q <= data;`
358
359			`endmodule`
360	40	unneback	`endif
361	3	unneback
362			`endif
363	5	unneback
364			`// LATCH`
365			`// For targtes not supporting LATCH use dff_sr with clk=1 and data=1`
366			`ifdef ALTERA
367	40	unneback
368			`ifdef LATCH
369			`define MODULE latch
370			module `BASE`MODULE ( d, le, q, clk);
371			`undef MODULE
372	5	unneback	`input d, le;`
373			`output q;`
374			`input clk;`
375			`dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));`
376			`endmodule`
377	40	unneback	`endif
378
379	5	unneback	`else
380	40	unneback
381			`ifdef LATCH
382			`define MODULE latch
383			module `BASE`MODULE ( d, le, q, clk);
384			`undef MODULE
385	5	unneback	`input d, le;`
386	48	unneback	`input clk;`
387			`always @ (le or d)`
388	60	unneback	`if (le)`
389	48	unneback	`d <= q;`
390	5	unneback	`endmodule`
391	15	unneback	`endif
392
393	40	unneback	`endif
394
395			`ifdef SHREG
396			`define MODULE shreg
397			module `BASE`MODULE ( d, q, clk, rst);
398			`undef MODULE
399
400	17	unneback	`parameter depth = 10;`
401			`input d;`
402			`output q;`
403			`input clk, rst;`
404
405			`reg [1:depth] dffs;`
406
407			`always @ (posedge clk or posedge rst)`
408			`if (rst)`
409			`dffs <= {depth{1'b0}};`
410			`else`
411			`dffs <= {d,dffs[1:depth-1]};`
412			`assign q = dffs[depth];`
413			`endmodule`
414	40	unneback	`endif
415	17	unneback
416	40	unneback	`ifdef SHREG_CE
417			`define MODULE shreg_ce
418			module `BASE`MODULE ( d, ce, q, clk, rst);
419			`undef MODULE
420	17	unneback	`parameter depth = 10;`
421			`input d, ce;`
422			`output q;`
423			`input clk, rst;`
424
425			`reg [1:depth] dffs;`
426
427			`always @ (posedge clk or posedge rst)`
428			`if (rst)`
429			`dffs <= {depth{1'b0}};`
430			`else`
431			`if (ce)`
432			`dffs <= {d,dffs[1:depth-1]};`
433			`assign q = dffs[depth];`
434			`endmodule`
435	40	unneback	`endif
436	17	unneback
437	40	unneback	`ifdef DELAY
438			`define MODULE delay
439			module `BASE`MODULE ( d, q, clk, rst);
440			`undef MODULE
441	15	unneback	`parameter depth = 10;`
442			`input d;`
443			`output q;`
444			`input clk, rst;`
445
446			`reg [1:depth] dffs;`
447
448			`always @ (posedge clk or posedge rst)`
449			`if (rst)`
450			`dffs <= {depth{1'b0}};`
451			`else`
452			`dffs <= {d,dffs[1:depth-1]};`
453			`assign q = dffs[depth];`
454	17	unneback	`endmodule`
455	40	unneback	`endif
456	17	unneback
457	40	unneback	`ifdef DELAY_EMPTYFLAG
458			`define MODULE delay_emptyflag
459	41	unneback	module `BASE`MODULE ( d, q, emptyflag, clk, rst);
460	40	unneback	`undef MODULE
461	17	unneback	`parameter depth = 10;`
462			`input d;`
463			`output q, emptyflag;`
464			`input clk, rst;`
465
466			`reg [1:depth] dffs;`
467
468			`always @ (posedge clk or posedge rst)`
469			`if (rst)`
470			`dffs <= {depth{1'b0}};`
471			`else`
472			`dffs <= {d,dffs[1:depth-1]};`
473			`assign q = dffs[depth];`
474			`assign emptyflag = !(\|dffs);`
475			`endmodule`
476	40	unneback	`endif
477	75	unneback
478			`ifdef ASYNC_REG_REQ_ACK
479			`define MODULE async_reg_req_ack
480			module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
481			`undef MODULE
482			`parameter data_width = 8;`
483			`input [data_width-1:0] d;`
484			`output [data_width-1:0] q;`
485			`input req_i;`
486			`output req_o;`
487			`input ack_i;`
488			`output ack_o;`
489			`input clk_a, rst_a, clk_b, rst_b;`
490
491			`reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync`
492			`wire rst;`
493
494			`always @ (posedge clk_a or rst_a)`
495			`if (rst_a)`
496			`q <= {data_width{1'b0}};`
497			`else`
498			`if (req_i)`
499			`q <= d;`
500

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